upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 510

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

510
16-bit data
transfer
8-bit
operation
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
3.
4.
MOVW
XCHW
ADD
ADDC
Mnemonic
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Only when rp = BC, DE or HL
Except “r = A”
control register (PCC).
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
AX, !addr16
!addr16, AX
AX, rp
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 29 INSTRUCTION SET
Note 3
Note 3
Note 3
Note 4
Note 4
User’s Manual U15947EJ3V1UD
Bytes
4
2
2
2
3
4
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
10
10
6
8
−
6
6
−
−
4
4
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
12 + 2m (addr16) ← AX
12 + 2n AX ← (addr16)
Note 2
9 + n
5 + n
9 + n
9 + n
9 + n
9 + n
5 + n
9 + n
9 + n
9 + n
10
10
−
8
8
8
8
−
−
−
−
8
−
−
5
−
8
−
−
5
rp ← word
(saddrp) ← word
sfrp ← word
AX ← (saddrp)
(saddrp) ← AX
AX ← sfrp
sfrp ← AX
AX ← rp
rp ← AX
AX ↔ rp
A, CY ← A + byte
(saddr), CY ← (saddr) + byte
A, CY ← A + r
r, CY ← r + A
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, CY ← A + (HL + byte)
A, CY ← A + (HL + B)
A, CY ← A + (HL + C)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
r, CY ← r + A + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A + (HL + B) + CY
A, CY ← A + (HL + C) + CY
CPU
) selected by the processor clock
Operation
Z AC CY
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Flag
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