upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 649

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

A/D
converter
Function
PFM: Power-fail
comparison
mode register
PFT: Power-fail
comparison
threshold
register
A/D conversion
operation
Power-fail
detection
function
Operating
current in
standby mode
Input range of
ANI0 to ANI7
Conflicting
operations
Noise
countermeasures
ANI0/P20 to
ANI7/P27
Input impedance
of ANI0 to ANI7
pins
Details of
Function
If data is written to PFM, a wait cycle is generated. Do not write data to PFM
when the CPU is operating on the subsystem clock and the X1 input clock is
stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT.
If data is written to PFT, a wait cycle is generated. Do not write data to PFT
when the CPU is operating on the subsystem clock and the X1 input clock is
stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT.
Make sure the period of <1> to <3> is 14
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, do not use the first conversion result after <3> in
this case.
The period from <4> to <7> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <6> to <7> is the conversion time set
using FR2 to FR0.
Make sure the period of <3> to <6> is 14
It is no problem if order of <3>, <4>, and <5> is changed.
<3> must not be omitted if the power-fail function is used.
The period from <7> to <11> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <9> to <11> is the conversion time set
using FR2 to FR0.
The A/D converter stops operating in the standby mode. At this time, the
operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter
mode register (ADM) to 0 (see Figure 13-2).
Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AV
or higher and AV
input to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
ADCR read has priority. After the read operation, the new conversion result is
written to ADCR.
ADM or ADS write has priority. ADCR write is not performed, nor is the
conversion end interrupt signal (INTAD) generated.
To maintain the 10-bit resolution, attention must be paid to noise input to the
AV
the output impedance of the analog input source, it is recommended that a
capacitor be connected externally, as shown in Figure 13-19, to reduce noise.
The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to
P27).
When A/D conversion is performed with any of ANI0 to ANI7 selected, do not
access port 2 while conversion is in progress; otherwise the conversion resolution
may be degraded.
If a digital pulse is applied to the pins adjacent to the pins currently used for A/D
conversion, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin
undergoing A/D conversion.
In this A/D converter, the internal sampling capacitor is charged and sampling is
performed for approx. one sixth of the conversion time.
Since only the leakage current flows other than during sampling and the current
for charging the capacitor also flows during sampling, the input impedance
fluctuates and has no meaning.
To perform sufficient sampling, however, it is recommended to make the output
impedance of the analog input source 10 kΩ or lower, or attach a capacitor of
around 100 pF to the ANI0 to ANI7 pins (see Figure 13-19).
REF
pin and pins ANI0 to ANI7. Because the effect increases in proportion to
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
SS
or lower (even in the range of absolute maximum ratings) is
Cautions
µ
µ
s or more.
s or more.
REF
p. 276
p. 276
p. 282
p. 282
p. 282
p. 282
p. 282
p. 282
p. 282
p. 282
p. 285
p. 285
p. 285
p. 285
p. 285
p. 286
p. 286
p. 286
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