upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 650

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

650
A/D
converter
Serial
interface
UART0
Function
AV
impedance
Interrupt
request flag
(ADIF)
Conversion
results just after
A/D conversion
start
A/D conversion
result register
(ADCR) read
operation
A/D converter
sampling time
and A/D
conversion start
delay time
Register
generating wait
cycle
UART mode
TXS0: Transmit
shift register 0
ASIM0:
Asynchronous
serial interface
operation mode
register 0
REF
Details of
Function
pin input
A series resistor string of several tens of kΩ is connected between the AV
AV
Therefore, if the output impedance of the reference voltage source is high, this will
result in a series connection to the series resistor string between the AV
AV
The interrupt request flag (ADIF) is not cleared even if the analog input channel
specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D
conversion result and ADIF for the pre-change analog input may be set just before
the ADS rewrite. Caution is therefore required since, at this time, when ADIF is
read immediately after the ADS rewrite, ADIF is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D
conversion operation is resumed.
The A/D conversion value immediately after A/D conversion starts may not fall
within the rating range if the ADCS bit is set to 1 within 14
was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures
such as polling the A/D conversion end interrupt request (INTAD) and removing
the first conversion result.
When a write operation is performed to the A/D converter mode register (ADM)
and analog input channel specification register (ADS), the contents of ADCR may
become undefined. Read the conversion result following conversion completion
before writing to ADM and ADS. Using a timing other than the above may cause
an incorrect conversion result to be read.
The A/D converter sampling time differs depending on the set value of the A/D
converter mode register (ADM). The delay time exists until actual sampling is
started after A/D converter operation is enabled.
When using a set in which the A/D conversion time must be strictly observed, care
is required for the contents shown in Figure 13-21 and Table 13-3.
Do not read data from the ADCR register and do not write data to the ADM, ADS,
PFM, and PFT registers while the CPU is operating on the subsystem clock and
while oscillation of the clock input to X1 is stopped.
If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode),
normal operation continues. If clock supply to serial interface UART0 is stopped
(e.g., in the STOP mode), each register stops operating, and holds the value
immediately before clock supply was stopped. The TxD0 pin also holds the value
immediately before clock supply was stopped and outputs it. However, the
operation is not guaranteed after clock supply is resumed. Therefore, reset the
circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception)
to start communication.
TXE0 and RXE0 are synchronized by the base clock (f
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may
not be initialized.
Do not write the next transmit data to TXS0 before the transmission completion
interrupt signal (INTST0) is generated.
At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear
TXE0 to 0, and then clear POWER0 to 0.
At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation, clear
RXE0 to 0, and then clear POWER0 to 0.
Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0
pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input,
reception is started.
SS
SS
pins.
pins, resulting in a large reference voltage error.
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
Cautions
XCLK0
µ
) set by BRGC0. To
s after the ADCE bit
REF
REF
and
and
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