upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 464

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upd78f0148m1gka1-9eu

Manufacturer Part Number
upd78f0148m1gka1-9eu
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
operation. When CLME is set to 1 by software at the end of the oscillation stabilization time (reset value of OSTS
register is 05H (2
automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode
and during the oscillation stabilization time.
464
Internal oscillation clock
Internal oscillation clock
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
Clock monitor status
Clock monitor status
(CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time)
CPU operation
(CLME = 1 is set when CPU clock operates on X1 input clock and before entering STOP mode)
X1 input clock
CPU operation
X1 input clock
(CPU clock)
RESET
CLME
16
CLME
/f
XP
)) of the X1 input clock, monitoring is started.
Monitoring
operation
Normal
operation
Normal
Monitoring
(4) Clock monitor status after STOP mode is released
(3) Clock monitor status after RESET input
Figure 23-3. Timing of Clock Monitor (2/4)
Reset
Oscillation
stopped
STOP
CHAPTER 23 CLOCK MONITOR
User’s Manual U15947EJ3V1UD
Monitoring stopped
Clock supply
Oscillation stabilization time
17 clocks
Oscillation stabilization time
(time set by OSTS register)
stopped
Monitoring stopped
Oscillation stabilization time
Normal operation (internal oscillation clock)
Normal operation
Monitoring
Set to 1 by software
Monitoring

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