upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 644

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

644
16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
Function
PRM01:
Prescaler mode
register 01
CR01n: 16-bit
timer capture/
compare
register 01n
CR00n, CR01n:
16-bit timer
capture/compare
registers 00n,
01n
PPG output
Pulse width
measurement
External event
counter
One-shot pulse
output:
Software trigger
One-shot pulse
output: External
trigger
Timer start
errors
Details of
Function
If the TI001 or TI011 pin is high level immediately after system reset, the rising
edge is immediately detected after the rising edge or both the rising and falling
edges are set as the valid edge(s) of the TI001 pin or TI011 pin to enable the
operation of 16-bit timer counter 01 (TM01). Care is therefore required when
pulling up the TI001 or TI011 pin. However, if the TI001 pin or TI011 pin is high
level when re-enabling operation after the operation has been stopped, the rising
edge is not detected.
When the valid edge of the TI011 pin is used, P06 cannot be used as the timer
output (TO01) pin. Moreover, when the TO01 pin is used, the valid edge of the
TI011 pin cannot be used.
To change the value of the duty factor (the value of the CR01n register) during
operation, see Caution 2 in Figure 7-20 PPG Output Operation Timing.
Values in the following range should be set in CR00n and CR01n:
0000H ≤ CR01n < CR00n ≤ FFFFH
The pulse generated through PPG output has a cycle of [CR00n setting value + 1],
and has a duty of [(CR01n setting value + 1)/(CR00n setting value + 1)].
In the PPG output operation, change the pulse width (rewrite CR01n) during TM0n
operation using the following procedure.
<1> Disable the timer output inversion operation by match of TM0n and CR01n
<2> Disable the INTTM01n interrupt (TMMK01n = 1)
<3> Rewrite CR01n
<4> Wait for 1 cycle of the TM0n count clock
<5> Enable the timer output inversion operation by match of TM0n and CR01n
<6> Clear the interrupt request flag of INTTM01n (TMIF01n = 0)
<7> Enable the INTTM01n interrupt (TMMK01n = 0)
To use two capture registers, set the TI00n and TI01n pins.
When reading the external event counter count value, TM0n should be read.
Do not set the OSPT0n bit to 1 again while the one-shot pulse is being output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
When using the one-shot pulse output of 16-bit timer/event counter 0n with a
software trigger, do not change the level of the TI00n pin or its alternate-function
port pin.
Because the external trigger is valid even in this case, the timer is cleared and
started even at the level of the TI00n pin or its alternate-function port pin, resulting
in the output of a pulse at an undesired timing.
Do not set the CR00n and CR01n registers to 0000H.
16-bit timer counter 0n starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC0n3 and TMC0n2 bits.
Do not input the external trigger again while the one-shot pulse is being output.
To output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
Do not set the CR00n and CR01n registers to 0000H.
16-bit timer counter 0n starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC0n3 and TMC0n2 bits.
An error of up to one clock may occur in the time required for a match signal to be
generated after timer start. This is because 16-bit timer counter 0n (TM0n) is
started asynchronously to the count clock.
(TOC0n4 = 0)
(TOC0n4 = 1)
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
Cautions
p. 172
p. 172
p. 177
p. 178
p. 178
p. 179
p. 180
p. 190
p. 193
p. 193
p. 194
p. 195
p. 195
p. 196
p. 197
p. 198
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