pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 125

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Result Phase
Multi-Track
Control
7
TABLE 5-19. SK Effect on READ DELETED DATA
Skip
(SK)
1. End of Track sector number from the command phase.
2. The number of the sector last operated on by controller.
3. Track number programmed in the command phase
0
0
1
1
(MT)
0
0
0
0
1
1
1
1
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
6
Deleted
Deleted
Normal
Normal
Type
Data
5
Head #
Bytes-Per-Sector Code
(HD)
0
0
1
1
0
0
1
1
Sector
Read?
Sector Number
Track Number
Head Number
Command
Y
Y
N
Y
4
TABLE 5-18. Result Phase Termination Values with No Error
End of Track (EOT)
Mark Bit 6
< EOT
= EOT
< EOT
= EOT
< EOT
= EOT
< EOT
= EOT
Sector Number
Control
of ST2
3
1
0
1
0
1
1
1
1
1
1
1
1
Sector #
Sector #
Sector #
Sector #
Sector #
Sector #
Sector #
Sector #
2
Sector Skipped
Sectors Read
Termination
Termination
No More
Normal
Normal
Result
1
Track Number Head Number Sector Number
Track
Track
Track
No Change
No Change
No Change
No Change
No Change
0
3
3
3
125
# + 1
# + 1
# + 1
5.7.12 The READ ID Command
The READ ID command finds the next available address
field and returns the ID bytes (track number, head number,
sector number, bytes-per-sector code) to the microproces-
sor in the result phase.
The controller reads the first ID Field header bytes it can
find and reports these bytes to the system in the result
bytes.
Command Phase
After the last command phase byte is written, the controller
waits the Delay Before Processing time (see TABLE 5-25
"Constant Multipliers for Delay Before Processing Factor
and Delay Ranges" on page 132) for the selected drive.
During this time, the drive motor must be turned on by en-
abling the appropriate drive and motor select disk interface
output signals via the bits of the Digital Output Register
(DOR). See Section 5.3.3 "Digital Output Register (DOR)"
on page 97.
First Command Phase Byte, Opcode
Second Command Phase Byte
X
7
0
See “Bit 6 - Modified Frequency Modulation (MFM)” on
page 116.
See “Second Command Phase Byte” on page 116 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
No Change
No Change
No Change
No Change
No Change
No Change
ID Information in Result Phase
MFM
X
6
1
0
X
5
0
Sector
Sector
Sector
Sector
X
4
0
1
1
1
1
2
2
2
2
# + 1
# + 1
# + 1
# + 1
X
3
1
Bytes-per-Sector
HD
2
0
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
Code
DS1
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1
1
DS0
0
0