pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 270

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Legacy Mode
LFSR
LSB
LSR
MCR
MSB
MSR
Non-Extended UART Operation Modes
NVM
P_BGDH and P_BGDL
PIO
P_MDR
Plug and Play
PM
PME
PMC1, PMC2 and PMC3
1. Main Status Register of the Floppy Disk Controller
2. Modem Status Register for UART1 for read opera-
In this mode, the interrupts and the base addresses
of the FDC, UARTs, KBC, RTC and the parallel
port of the PC87308VUL are configured as in earli-
er SuperI/O chips.
The Linear Feedback Shift Register. In Plug and
Play mode, this register is used to prepare the chip
for operation in Plug and Play (PnP) mode.
Least Significant Byte or Bit.
Line Status Register for UART1 (logical device 6,
offset 05h) and for the UART2 in Non-Extended
modes only (logical device 5, bank 0, offset 05h).
Modem Control Register for UART1 (logical device
6, offset 04h) and for the UART2 (logical device 5,
bank 0, offset 04h).
Most Significant Byte or Bit.
Two expressions:
(FDC) (logical device 3, offset 4h).
tions (logical device 6, offset 06h) and for the
UART2 (logical device 5, bank 0, offset 06h).
These UART operation modes support only UART
operations that are standard for 15450 or 16550A
devices.
Non-volatile memory.
Pipeline Baud rate Generator Divisor buffer (High
and Low bytes) for UARTs. (Logical devices 5 and
6, bank 5, offsets 01h and 00h, respectively.)
Programmable Input/Output.
Pipeline Mode Register for UARTs. (Logical devic-
es 5 and 6, bank 5, offset 02h.)
A design philosophy and a set of specifications that
describe hardware and software changes to the PC
and its peripherals that automatically identify and
arbitrate resource requirements among all devices
and buses on the system. Plug and Play is some-
times abbreviated as PnP.
Power Management.
Power Management Event.
Power Management Control registers of logical de-
vice 8 at offsets 02h, 03h and 04h, respectively.
Glossary
270
PnP
PnP Mode
PP Confg0
Precompensation
RBR
RCCFG
RLC
RLE
RLR
RSR
RTC
RXDR
RXFLV
SCI
SCR
SH_FCR
SH_LCR
Sharp IR
Sometimes used to indicate Plug and Play.
In this mode, the interrupts, the DMA channels and
the base address of the FDC, UARTs, KBC, RTC,
GPIO,
PC87308VUL are fully Plug and Play.
Internal configuration register of the Parallel Port in
Extended Capabilities Port (ECP) modes. (Logical
device 4, second level offset 05h.)
Also called write precompensation, is a way of pre-
conditioning the
the effects of bit shift on the data as it is written to
the disk surface.
Receiver Buffer Register for UART1, read opera-
tions only (logical device 6, offset 00h, divisor latch
registers not accessible, bit 7 of LCR = 0).
Consumer Remote Control Configuration register
for the UART2. (Logical device 5, bank 7, offset
02h.)
Run Length Count byte for parallel ports.
Run Length Expander for parallel ports.
RAM Lock Register for Advanced Power Control
(APC). (Logical device 2, offset 47h.)
Internal Receiver Shift Register for UART1.
Real-Time Clock.
Receiver Data Register for read cycles for the
UART2. (Logical device 5, bank 0, offset 00h.)
Reception FIFO Level for the UART2. (Logical de-
vice 5, bank 2, offset 07h.)
Scratch Register for UART1 (logical device 6, offset
07h) and for the UART2 in UART operation mode
(logical device 5, bank 0, offset 07h).
Shadow of the FIFO Control Register (FCR) for the
UART2 for read operations. (Logical device 5, bank
3, offset 02h.)
Shadow of the Line Control Register (LCR) for the
UART2 for read operations. (Logical device 5, bank
3, offset 01h.)
Sharp Infrared.
System Control Interrupt.
APC
and
WDATA
the
output signal to adjust for
Parallel
Port
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