pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 96

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

www.national.com
When the controller is ready to receive a command byte, the
MSR returns a value of 80h (Request for Master (RQM, bit
7) bit is set). The MSR is guaranteed to return the 80h value
within 250 sec after a hardware or software reset.
All other user addressable registers other than the Main
Status Register (MSR) and Data Register (FIFO) can be ac-
cessed at any time, even during software reset.
5.3 THE FDC REGISTERS
The FDC registers are mapped to the offset address shown
in TABLE 5-1 "The FDC Registers and Their Addresses",
with the base address range provided by the on-chip ad-
dress decoder. For PC-AT or PS/2 applications, the offset
address range of the diskette controller is 00h through 07h
from the index of logical device 3.
The FDC supports two system operation modes: PC-AT
drive mode and PS/2 drive mode (MicroChannel systems).
Section 5.1.2 "System Operation Modes" on page 92 de-
scribes each mode and “Bit 2 - PC-AT or PS/2 Drive Mode
Select” on page 37 describes how each is enabled.
Unless specifically indicated otherwise, all fields in all regis-
ters are valid in both drive modes.
The FDC supports plug and play, as follows:
5.3.1
Status Register A (SRA) monitors the state of assigned IRQ
signal and some of the disk interface signals. SRA is a read-
only register that is valid only in PS/2 drive mode.
TABLE 5-1. The FDC Registers and Their Addresses
Symbol
DOR
MSR
FIFO
DSR
CCR
SRA
SRB
TDR
DIR
The FDC interrupt can be routed on one of the following
ISA interrupts: IRQ3-IRQ7, IRQ9-IRQ12 and IRQ15
(see PNP2 register).
The FDC DMA signals can be routed to one of three 8-
bit ISA DMA channels (see PNP2 register); and its base
address is software configurable (see FBAL and FBAH
registers).
Upon reset, the DMA of the FDC is routed to the DRQ2
and DACK2 pins.
-
Status Register A (SRA)
Status Register A
Status Register B
Digital Output Register
Tape Drive Register
Main Status Register
Data Rate Select Register 1
Data Register (FIFO)
(Bus in TRI-STATE)
Digital Input Register
CCR Configuration
Control Register
Description
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
A2 A1 A0
0
0
0
0
1
1
1
1
1
Offset
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
0
1
0
1
1
R/W
R/W
R/W
R/W
W
W
R
R
R
R
X
96
SRA can be read at any time while PS/2 drive mode is ac-
tive. In PC-AT drive mode, all bits are in TRI-STATE during
a microprocessor read.
Bit 0 - Head Direction
Bit 1 - Write Protect (WP)
Bit 2 - Beginning of Track (INDEX)
Bit 3 - Head Select
Bit 4 - At Track 0 (TRK0)
0
7
This bit indicates the direction of the head of the Floppy
Disk Drive (FDD). Its value is the inverse of the value of
the DIR interface output signal.
0: DIR is not active, i.e., the head of the FDD steps
1: DIR is active, i.e., the head of the FDD steps in-
This bit indicates whether or not the selected Floppy
Disk Drive (FDD) is write protected. Its value reflects the
status of the WP disk interface input signal.
0: WP is active, i.e., the FDD in the selected drive is
1: WP is not active, i.e., the FDD in the selected drive
This bit indicates the beginning of a track. Its value re-
flects the status of the INDEX disk interface input signal.
0: INDEX is active, i.e., it is the beginning of a track.
1: INDEX is not active, i.e., it is not the beginning of a
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected by the head. Its value is the inverse of
the HDSEL disk interface output signal.
0: HDSEL is not active, i.e., the head of the FDD se-
1: HDSEL is active, i.e., the head of the FDD selects
This bit indicates whether or not the head of the Floppy
Disk Drive (FDD) is at track 0. Its value reflects the sta-
tus of the TRK0 disk interface input signal.
0: TRK0 is active, i.e., the head of FDD is at track 0.
1: TRK0 is not active, i.e., the head of FDD is not at
IRQ Pending
6
outward. (Default)
ward.
write protected.
is not write protected.
track.
lects side 0. (Default)
side 1.
track 0.
Reserved
0
5
FIGURE 5-5. SRA Register Bitmap
Step
4
TRK0
0
3
PS/2 Drive Mode
Head Select
2
INDEX
1
WP
0
0
Reset
Required
Head Direction
Status Register
Offset 00h
A (SRA)