pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 67

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

4.4.3
The APC may activate the host power supply when the fol-
lowing “wake-up” events occur:
The PC may be powered down by the following events:
The SWITCH Input Signal
This signal provides two events: Switch On and Switch Off.
In both, the physical switch line is debounced, i.e., the sig-
nal state is transferred only after 14 to 16 msec without tran-
sitions, which ensures the switch is no longer bouncing. See
FIGURE 4-13.
Switch-On Event - Detection of a high to low transition on
Switch-Off Event - Detection of a high to low transition on
Switch-Off Delay - When the Switch-Off Delay Enable bit
Physical On/Off switch is depressed and V
sent.
Preprogrammed wake-up time arrives.
Communications input is detected on a modem.
Ring signal is detected at a telephone input jack.
General Purpose Power Management wake-up event
occurs.
Physical On/Off switch is depressed with V
or depressed continuously for longer than 4 seconds.
Software controlled power down.
Fail-safe power down in the event of power-down soft-
ware hang-up. (See “Switch-Off Event” below.)
ONCTL is active but V
(See ONCTL description).
the debounced SWITCH input pin, when V
exist. The Switch-On event is masked (not detected) for
one to two seconds after V
The Switch-On event sets the Switch-On event detect
bit to 1 (bit 2 of APSR1).
the debounced SWITCH input pin, when V
The Switch-Off event sets the Switch-Off Event Detect
bit (bit 5 in APSR) to 1.
(bit 6 in register APCR2) is 0, the Switch-Off event pow-
ers the system off immediately, i.e., the ONCTL output
pin is deactivated immediately.
SWITCH
V
V
System Power-Up and Power-Off Activation
Event Description
CCH
DD
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
DD
DD
doesn’t exist for 500 ms
is removed.
Edge or Trigger POR Select
APCR1 Register, Bit 2
FIGURE 4-13. Switch Event Detector
APCR1 Register, Bit 3
DD
DD
Level POR Clear
DD
DD
exists.
does not
present,
is ab-
Debounce
V
67
DD
When the Switch-Off Delay Enable bit is 1, occurrence of a
Switch-Off event will trigger a Fail-safe Timer countdown of
5 or 21 seconds. (Countdown length is set by bit 1 of the
APCR1 register. See Section 4.5.1 "APC Control Register
1 (APCR1)" on page 70.) If it is allowed to complete this
countdown (i.e., no reset or retrigger occurs while counting
down), the Fail-safe Timer sets the ONCTL signal high (in-
active). This Fail-safe Timer countdown may also be trig-
gered (or retriggered if a countdown is already in progress)
by writing a 1 to bit 0 of APCR1. Triggering sets the timer to
its initial countdown value and starts the countdown se-
quence. Switch-Off events occurring while a countdown is
in progress will not affect the countdown.
Switch-Off Event detection activates the Power-Off Re-
quest (POR) that triggers a user-defined interrupt routine to
conduct housekeeping activities prior to powering down.
(The user may also detect the Switch-Off Event by polling
the Switch-Off Detect bit, rather than by using the interrupt
routine). The user must ensure that the power-off routine
duration does not exceed the 5 or 21 second Switch-Off De-
lay. If required, a user routine may deactivate the count-
down by setting the Fail-safe Timer Reset Command bit, (bit
6 of APCR1). Setting this bit will stop and reset the Fail-safe
Timer, thus preventing the fail-safe timer from causing pow-
er off before completion.
If the power-off routine gets “hung up”, and the timer was
not stopped and reset, then after the delay time has elapsed
the timer will conclude its countdown and activate power off
(deactivate ONCTL).
The Fail-safe Timer is stopped, and reset, by writing 1 to the
Fail-safe Timer reset bit (bit 6 of APCR1). Switch-off events
detected while the timer is already counting are ignored. If,
V
timer is stopped and reset, and ONCTL is not deactivated.
POR may be asserted on a Switch-Off Event. It can be con-
figured as either edge or level triggered, according to the
APCR1 register, bit 2. In edge mode, it is a negative pulse,
and in level mode it remains asserted until cleared by a level
POR Clear Command (bit 3 of the APCR1 register, see FIG-
URE 4-12 "POR, SCI and ONCTL Generation" on page
66). Selection of POR on the GPIO22/POR pin is via the Su-
perI/O Configuration 2 register (at index 22h). Selection of
the POR output buffer is via GPIO22 output buffer control
bits (Port 2 Output Type and Port 2 Pull-up Control regis-
ters). See TABLE 9-2 "The GPIO Registers, Bank 0" on
page 216.
Exists
DD
goes down while the Fail-safe Timer is counting, the
Detector
Falling
Edge
POR
Switch-On Event
Switch-Off Event
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