pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 3

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

— A Fail-safe event occurs (power-save mode detected
— Software turns power off
— Any one of 10 programmable Power Management
Two Serial Ports (UART1 and 2) that provide:
— Fully compatible with the 16550A and the 16450
— Extended UART mode
— 13 IRQ channel options
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
An enhanced UART with IR interface on the UART2 that
supports:
— IrDA 1.0-SIR
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
— Consumer Remote Control circuitry
— DMA handshake signal routing for either 1 or 2 chan-
— A PnP compatible external transceiver
A bidirectional parallel port that includes:
— A modifiable address that is referenced by a 16-bit
— Software or hardware control
— 13 IRQ channel options
— Four 8-bit DMA channel options
— Demand mode DMA support
— An Enhanced Parallel Port (EPP) that is compatible
— An Enhanced Parallel Port (EPP) that also supports
— Support for an Enhanced Parallel Port (EPP) as
— An Extended Capabilities Port (ECP) that is IEEE
— Selection of internal pull-up or pull-down resistor for
— Reduction of PCI bus utilization by supporting a de-
— A protection circuit that prevents damage to the par-
— Output buffers that can sink and source14 mA
Three general-purpose pins for three separate program-
mable chip select signals, as follows:
— Can be programmed for game port control
— The Chip Select 0 (CS0) signal produces open drain
— The Chip Select 1 (CS1) and 2 (CS2) signals have
— Decoding of chip select signals depends on the ad-
but the system is hung up)
trigger events occur
nels
programmable register
with the new version EPP 1.9, and is IEEE 1284
compliant
version EPP 1.7 of the Xircom specification
mode 4 of the Extended Capabilities Port (ECP)
1284 compliant, including level 2
Paper End (PE) pin
mand DMA mode mechanism and a DMA fairness
mechanism
allel port when a printer connected to it powers up or
is operated at high voltages
output and is powered by the V
push-pull buffers and are powered by the main V
dress and the Address Enable (AEN) signals, and
can be qualified using the Read (RD) and Write
(WR) signals.
CCH
DD
Highlights
3
24 single-bit GPIO ports:
— Modifiable addresses that are referenced by a 16-bit
— Programmable direction for each signal (input or out-
— Programmable drive type for each output pin (open-
— Programmable option for internal pull-up resistor on
— Configuration-Lock options
— Several signals may be selected as interrupt triggers
— A back-drive protection circuit
An X-bus data buffer that connects the 8-bit X data bus
to the ISA data bus
Clock source options:
— Source is a 32.768 KHz crystal - an internal frequen-
— Source may be either a 48 MHz or 24 MHz clock in-
Enhanced Power Management (PM), including:
— Special configuration registers for power down
— WATCHDOG timer for power-saving strategies
— Reduced current leakage from pins
— Low-power CMOS technology
— Ability to shut off clocks to all modules
— LED control powered by V
General features include:
— All accesses to the SuperI/O chip activate a Zero
— Access to all configuration registers is through an In-
— 160-pin Plastic Quad Flatpack (PQFP) package
programmable register
put)
drain or push-pull)
each input pin
cy multiplier generates all the required internal fre-
quencies.
put signal.
Wait State (ZWS) signal, except for accesses to the
Enhanced Parallel Port (EPP) and to configuration
registers
dex and a Data register, which can be relocated
within the ISA I/O address space
CCH
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