pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 58

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Bit 3 - Unused
Bit 4 - Update-Ended Interrupt Enable (UIE)
Bit 5 - Alarm Interrupt Enable (AIE)
Bit 6 - Periodic Interrupt Enable (PIE)
Bit 7 - Set Mode (SET)
4.2.3
This register indicates the status of interrupt request flags.
Bits 3-0 - Reserved
Bit 4 - Update-Ended Interrupt Flag (UF)
7
This bit is defined as “Square Wave Enable” by the
MC146818 and is not supported by the RTC. This bit is
always read as 0.
Master reset forces this read/write bit to 0.
0: Disables generation of the Update-Ended interrupt.
1: Enables generation of the Update-Ended interrupt.
Master reset forces this read/write bit to 0.
0: Disables generation of the alarm interrupt.
1: Enables generation of the Alarm interrupt. The
Master reset forces this read/write bit to 0.
0: Disables generation of the Periodic interrupt.
1: Enables generation of the Periodic interrupt. Bits 3-
Master reset does not affect this read/write bit.
0: The timing updates occur normally.
1: The user copy of time is “frozen”, allowing the time
These bits are reserved and always return 0000.
Master reset forces this read-only bit to 0. In addition,
this bit is reset to 0 when this register is read.
0: No update has occurred since the last read.
1: Time registers have been updated.
IRQF
6
0
This interrupt is generated at the time an update
occurs.
alarm interrupt is generated immediately after a
time update in which the Seconds, Minutes, Hours
Day-of-month and Month time equal their respec-
tive alarm counterparts.
0 of Control Register A (CRA) determine the rate of
the Periodic interrupt.
registers to be accessed without regard for an oc-
currence of an update.
RTC Control Register C (CRC)
PF
5
0
FIGURE 4-6. CRC Register Bitmap
AF
4
0
UF
3
0
0
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
2
0
0
1
0
0
Reserved
0
0
0
Power-Up
Reset
Required
RTC Control
Register C
Index 0Ch
(CRC)
58
Bit 5 - Alarm Interrupt Flag (AF)
Bit 6 - Periodic Interrupt Flag (PF)
Bit 7 - Interrupt Request Flag (IRQF)
4.2.4
This register indicates the validity of the RTC RAM data.
Bits 6-0 - Reserved
Bit 7 - Valid RAM and Time (VRT)
WARNING:
7
0
Master reset forces this read-only bit to 0.
0: No alarm was detected since the last read.
1: An alarm condition was detected. This bit is reset
Master reset forces this read-only bit to 0. In addition,
this bit is reset to 0 when this register is read.
0: Indicates no transition occurred on the selected tap
1: A transition occurred on the selected tap of the di-
This read-only bit is the inverse of the value on the IRQ
output signal of the RTC/APC.
0: IRQ is inactive (high).
1: IRQ is active (low) and any of the following condi-
These bits are reserved and always return 0.
The VRT bit senses the voltage that feeds this logical
device (V
was too low since the last time this bit was read. If it was
too low, the RTC and RAM data are not valid.
This read-only bit is set to 1 when this register is read.
0: The voltage that feeds the APC/RTC logical device
1: The RTC and RAM data are valid.
If V
may reset this bit.
VRT
6
0
0
to 0 when this register is read.
since the last read.
vider chain.
tions exists: both PIE and PF are 1; both AIE and
AF are 1; both UIE and UF are 1. (PIE, AIE and
UIE are bits 6, 5 and 4, respectively of the CRB
register.)
was too low.
CCH
RTC Control Register D (CRD)
5
0
0
FIGURE 4-7. CRD Register Bitmap
ramps down at a rate exceeding 1 V/msec, it
CCH
4
0
0
3
0
0
or V
2
0
0
BAT
Reserved
1
0
0
) and indicates whether or not it
0
0
0
Power-Up
Reset
Required
RTC Control
Register D
Index 0Dh
(CRD)