pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 83

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bit 5 - GPIO13 Enable (GPIO13_E)
Bit 6 - GPIO10 Enable (GPIO10_E)
Bit 7 - P12 Enable (P12_E)
4.7.6
This register is reserved. Read returns 0.
4.7.7
This register is reserved. Read returns 0.
4.7.8
This register is reserved. Read returns 0.
4.7.9
Upon first power Up and Master Reset, these bits are initial-
ized to 0.
.
Bit 0 - PME1 Enable (PME1_E)
7
0
0: GPIO13 Status bit is ignored (bit 5 of the
1: When the GPIO13 Status bit is 1:
0: GPIO10 Status bit is ignored (bit 6 of the
1: When the GPIO10 Status bit is 1:
0: P12 Status bit is ignored (bit 7 of the GP1_STS0
1: When the P12 Status bit is 1:
0: PME1 Status bit is ignored (bit 0 of the GP1_STS0
1: Activate the POR pin, when the PME1 Status bit is 1,
When PME1 is not selected on its corresponding pin,
this bit should be 0.
6
0
P12_E
GP1_STS0 register).
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
GP1_STS0 register).
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
register).
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
register).
regardless of bit 0 of the PM1_CNT_LOW register.
FIGURE 4-44. GP2_EN0 Register Bitmap
General Purpose 1 Enable 1 Register
(GP1_EN1), Offset 05h
General Purpose 1 Enable 2 Register
(GP1_EN2), Offset 06hr
General Purpose 1 Enable 3 Register
(GP1_EN3), Offset 07h
General Purpose 2 Enable 0 Register
(GP2_EN0)
5
0
GPIO10_E
GPIO13_E
4
0
3
0
GPIO12 Enable
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
2
IRRX2_E
0
0
1
IRRX1_E
0
PME2_E
0
Power-Up
Reset
Required
PME1_E
General Purpose 2
Enable Register
(GP2_EN0)
Offset 08h
83
Bit 1 - PME2 Enable (PME2_E)
Bit 2 - IRRX1 Enable (IRRX1_E)
4.7.10 Bit 3 - IRRX2 Enable (IRRX2_E)
Bit 4 - GPIO12 Enable (GPIO12_E)
Bit 5 - GPIO13 Enable (GPIO13_E)
Bit 6 - GPIO10 Enable (GPIO10_E)
Bit 7 - P12 Enable (P12_E)
4.7.11 SMI Command Register (SMI_CMD), Offset 0Ch
This is an 8-bit read/write register. The data held in this reg-
ister has no affect on the PC87317. Any write to this register
sets bit 5 of the ACPI Support register (see Logical Device
8). This can assert POR.
0: PME2 Status bit is ignored (bit 1 of the GP1_STS0
1: Activate the POR pin, when the PME2 Status bit
When PME2 is not selected on its corresponding pin,
this bit should be 0.
0: IRRX1 Status bit is ignored (bit 2 of the GP1_STS0
1: Activate the POR pin, when the IRRX1 Status bit
When IRRX1 is not selected on its corresponding pin,
this bit should be 0.
0: IRRX2 Status bit is ignored (bit 3 of the GP1_STS0
1: Activate the POR pin, when the IRRX2 Status bit
When IRRX2 is not selected on its corresponding pin,
this bit should be 0.
0: GPIO12 Status bit is ignored (bit 4 of the
1: Activate the POR pin, when the GPIO12 Status bit is
0: GPIO13 Status bit is ignored (bit 5 of the
1: Activate the POR pin, when the GPIO13 Status bit is
0: GPIO10 Status bit is ignored (bit 6 of the
1: Activate the POR pin, when the GPIO10 Status bit is
0: P12 Status bit is ignored (bit 7 of the
1: Activate the POR pin, when the P12 Status bit is 1,
register).
is 1, regardless of bit 0 of the PM1_CNT_LOW
register.
register).
is 1, regardless of bit 0 of the PM1_CNT_LOW
register.
register)
is 1, regardless of bit 0 of the PM1_CNT_LOW
register.
GP1_STS0 register).
1, regardless of bit 0 of the PM1_CNT_LOW register.
GP1_STS0 register)
1, regardless of bit 0 of the PM1_CNT_LOW register.
GP1_STS0 register).
1, regardless of bit 0 of the PM1_CNT_LOW register.
GP1_STS0 register).
regardless of bit 0 of the PM1_CNT_LOW register.
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