pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 254
pc87317vul
Manufacturer Part Number
pc87317vul
Description
Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87317VUL.pdf
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t
t
t
t
t
t
t
t
t
t
KIP
KKP
KQP
QKP
QPP
QQP
QRP
RQP
TQP
TT
Symbol
1. One DMA transaction takes six clock cycles.
2. t
3. Only in case of pending DRQ.
4. The active edge of RD or WR and TC is recognized only when DACK is active.
DRQ
DACK
RD, WR
TC
(max)." on page 244.
CP
is defined in TABLE 14-42 "Clock TimingFor the 14.31818MHz clock, required tolerance is 200 ppm
DACK Inactive Pulse Width
DACK Active Pulse Width
DACK Active Edge to DRQ Inactive
DRQ to DACK Active Edge
DRQ Period
DRQ Inactive Non-Burst Pulse Width
DRQ to RD, WR Active
RD, WR Active Edge to DRQ Inactive
TC Active Edge to DRQ Inactive
TC Active Pulse Width
t
QKP
t
QRP
Parameter
FIGURE 14-15. ECP DMA Timing
TABLE 14-52. ECP DMA Timing
Device Specifications
1 2
4
254
t
KKP
t
KQP
t
QPP
t
TT
Min
330
300
25
65
10
15
50
t
TQP
t
RQP
65 + (6 x 32 x t
400
Max
65
75
3
t
KIP
CP
t
QQP
)
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Unit
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