pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 221

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

10.2.6 Power Management Control 2 Register (PMC2)
This register selects the SuperI/O Clock source, enables
the Clock Multiplier and monitors Multiplier Clock Status.
Bits 1,0 - SuperI/O Clock Source
These bits determine the SuperI/O clock source.
The reset value of bit 0 is determined by the CFG0 Strap-
ping (See Section 2). When CFG0 is 0, the reset value is 1;
when CFG0 is 1, this bit’s reset value is 0.
Bit 2 - Clock Multiplier Enable
Bits 6-3 - Reserved
Bit 7 - Valid Multiplier Clock Status
PMC2
7
Bits
1 0
0 0
0 1
1 0
1 1
0: On-chip clock multiplier is disabled. (Default)
1: On-chip clock multiplier is enabled.
This bit is read only.
0: On-chip clock (clock multiplier output) is frozen.
1: On-chip clock (clock multiplier output) is stable and
TABLE 10-2. SuperI/O Clock Source selection
Valid Multiplier Clock Status
0
6
toggling.
FIGURE 10-6. PMC2 Register Bitmap
The 24 MHz clock is fed via the X1 pin
Reserved
The 48 MHz clock is fed via the X1 pin
The clock source is the on-chip clock multiplier
0
5
0
4
Reserved
0
3
0
2
SuperI/O Clock Source
Clock Multiplier Enable
1
1
X
0
SuperI/O Clock Source
Reset
Required
Power Management
Control 2 Register
Power Management (Logical Device 8)
Index 03h
(PMC2)
221
10.2.7 Power Management Control 3 Register (PMC3)
This register enables and monitors functions and devices.
Hard reset initializes this register to 0Eh.
Bit 0 - Power Management Timer CLock Enable
Bit 1 - Parallel Port Clock Enable
Bit 2 - UART2 Clock Enable
Bit 3 - UART1 Clock Enable
0
7
0: The clock is disabled.
1: The clock is enabled.
This bit is ANDed with bit 1 of the SuperI/O Parallel Port
Configuration register at index F0h of logical device 4. If
either bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
0: The clock is disabled.
1: If bit 1 of the SuperI/O Parallel Port Configuration
This bit is ANDed with bit 1 of the SuperI/O UART2 Con-
figuration register at index F0h of logical device 5. If ei-
ther bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
0: The clock is disabled.
1: If bit 1 of the SuperI/O UART2 Configuration regis-
This bit is ANDed with bit 1 of the SuperI/O UART1 Con-
figuration register at index F0h of logical device 6. If, ei-
ther bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
0: The clock is disabled.
1: If bit 1 of the SuperI/O UART1 Configuration regis-
UART1 busy Indicator
0
6
The PM Timer registers (see Fixed ACPI registers)
are not accessible. Reads are ignored.
The TMR_STS and the TMR_EN bits (in PM1
Event registers) are read-only bits. Read returns 0.
The PM Timer registers (see Fixed ACPI registers)
are accessible.
The TMR_STS and the TMR_EN bits (in PM1
Event registers) are functional.
register is set to 1, the clock is enabled. (Default)
ter is set to 1, the clock is enabled. (Default)
ter is set to 1, the clock is enabled. (Default)
UART2 Busy Indicator
FIGURE 10-7. PMC3 Register Bitmap
0
5
0
4
Reserved
1
3
UART1 Clock Enable
1
2
UART2 Clock Enable
1
1
Parallel Port Clock Enable
0
0
Reset
Required
PM Timer Clock Enable
Power Management
Control 3 Register
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Index 04h
(PMC3)