pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 138

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

www.national.com
In SPP Extended mode, parallel data transfer is bi-direc-
tional. TABLE 6-12 "Parallel Port Pinout" on page 160 lists
the output signals for the standard 25-pin, D-type connec-
tor.
6.2.1
In all Standard Parallel Port (SPP) modes, port operation is
controlled by the registers listed in TABLE 6-3 "Standard
Parallel Port (SPP) Registers".
All register bit assignments are compatible with the assign-
ments in existing SPP devices.
A single Data Register DTR is used for data input and out-
put (see Section 6.2.2 "SPP Data Register (DTR)"). The di-
rection of data flow is determined by the system setting in
bit 5 of the Control Register CTR.
Configuration at
Configuration at
Configuration
System Initial-
System Initial-
Run-Time Re-
configuration
ization with
(Dynamic)
IRQ5,7
Signal
1. Section 2.7.1 "SuperI/O Parallel Port Configuration Register" on page 41 describes the bits of the SuperI/O Par-
2. See Section 6.5.12 "Extended Control Register (ECR)" on page 150
3. Before modifying this bit, set bit 4 of the SuperI/O Parallel Port configuration register at index F0h to 1.
4. Use bit 7 of the Control2 register at second level offset 2 of the parallel port to further specify compatibility. See
(Static)
ization
SLIN
AFD
STB
INIT
Time
allel Port configuration register.
Section 6.5.17 "Control2 Register" on page 152.
SPP Modes Register Set
TABLE 6-2. Parallel Port Reset States
Reset Control
EPP Revision 1.7
EPP Revision 1.9
EPP Revision 1.7
EPP Revision 1.9
Operation Mode
SPP Compatible
SPP Compatible
SPP Extended
SPP Extended
ECP (Default)
MR
MR
MR
MR
MR
PP FIFO
State After Reset
TABLE 6-1. Parallel Port Mode Selection
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Configuration Register
SuperI/O Parallel Port
Zero
Parallel Port (Logical Device 4)
(Index F0h)
7 6 5
0 0 0
0 0 1
0 1 0
1 0 0
1 1 1
1 1 1
1 0 0
1 1 1
0 1 1
or
or
138
1
TABLE 6-2 "Parallel Port Reset States" on page 138 lists
the reset states for handshake output pins in this mode.
6.2.2
This bidirectional data port transfers 8-bit data in the direc-
tion determined by bit 5 of SPP register CTR at offset 02h
and mode.
The read or write operation is activated by the system RD
and WR strobes.
TABLE 6-4 "SPP DTR Register Read and Write Modes"
tabulates DTR register operation.
TABLE 6-3. Standard Parallel Port (SPP) Registers
Offset
00h
01h
02h
03h
Extended Control Register
(ECR) of the Parallel Port
SPP Data Register (DTR)
(Offset 402h)
Name
DTR
CTR
STR
7 6 5
0 0 0
0 1 0
0 0 1
1 0 0
0 1 1
-
-
-
-
2
Description
Control
Status
Data
-
of the Parallel Port
Control2 Register
(Offset 02h)
4
0
1
-
-
-
-
-
-
-
-
TRI-STATE
R/W
R/W
R/W
R
3
4
4
4
4
4
-
-
-
-
-