pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 140

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Bit 5 - PE Status
Bit 6 - ACK Status
Bit 7 - Printer Status
6.2.4
The control register provides all the output signals that con-
trol the printer. Except for bit 5, it is a read and write register.
Normally when the Control Register (CTR) is read, the bit
values are provided by the internal output data latch. These
bit values can be superseded by the logic level of the STB,
AFD, INIT, and SLIN signals, if these signals are forced high
or low by external voltage. To force these signals high or
low the corresponding bits should be set to their inactive
states (e.g., AFD, STB and SLIN should all be 0; INIT
should be 1).
Section 6.3.10 "EPP Mode Transfer Operations" on page
143 describes the transfer operations that are possible in
EPP modes.
Bit 0 - Data Strobe Control
1
7
This bit reflects the current state of the printer paper end
signal (PE). The printer sets this bit high when it detects
the end of the paper.
0: Printer has paper.
1: End of paper in printer.
This bit reflects the current state of the printer acknowl-
edge signal, ACK. The printer pulses this signal low af-
ter it has received a character and is ready to receive
another one. This bit follows the state of the ACK pin.
0: Character reception complete.
1: No character received.
This bit reflects the current state of the printer BUSY sig-
nal. The printer sets this bit low when it is busy and can-
not accept another character.
This bit is the inverse of the (BUSY/WAIT) pin.
0: Printer busy.
1: Printer not busy.
Bit 0 directly controls the data strobe signal to the printer
via the STB signal.
This bit is the inverse of the STB signal.
FIGURE 6-3. CTR Register Bitmap (SPP Mode)
Reserved
1
6
SPP Control Register (CTR)
Reserved
0
5
Direction Control
0
4
Interrupt Enable
0
3
1
Parallel Port Input Control
2
Printer Initialization Control
0
1
Automatic Line Feed Control
0
0
Reset
Required
Data Strobe Control
SPP Control Register
Parallel Port (Logical Device 4)
Offset 02h
(CTR)
140
Bit 1 - Automatic Line Feed Control
Bit 2 - Printer Initialization Control
Bit 3 - Select Input Signal Control
Bit 4 - Interrupt Enable
Bit 5 - Direction Control
This bit directly controls the automatic line feed signal to
the printer via the AFD pin. Setting this bit high causes
the printer to automatically feed after each line is print-
ed.
This bit is the inverse of the AFD signal.
0: No automatic line feed. (Default)
1: Automatic line feed
Bit 2 directly controls the signal to initialize the printer via
the INIT pin. Setting this bit to low initializes the printer.
The value of the INIT signal reflects the value of this bit.
The default setting of 1 on this bit prevents printer initial-
ization in SPP mode, and enables ECP mode after re-
set.
0: Initialize Printer.
1: No action (Default).
This bit directly controls the select in signal to the printer
via the SLIN signal. Setting this bit high selects the print-
er.
It is the inverse of the SLIN signal.
This bit must be set to 0 before enabling the EPP or
ECP mode.
0: Printer not selected. (Default)
1: Printer selected and online.
Bit 4 controls the interrupt generated by the ACK signal.
Its function changes slightly depending on the parallel
port mode selected.
In ECP mode, this bit should be set to 0.
In the following description, IRQx indicates an interrupt
allocated for the parallel port.
0: In SPP Compatible, SPP Extended and EPP
1: In SPP Compatible mode, IRQx follows ACK transi-
This bit determines the direction of the parallel port in
SPP Extended mode only. In the (default) SPP Compat-
ible mode, this bit has no effect, since the port functions
for output only.
This is a read/write bit in EPP modes. In SPP modes it
is a write only bit. A read from it returns 1.
In SPP Compatible mode and in EPP modes it does not
control the direction. See TABLE 6-4 "SPP DTR Regis-
ter Read and Write Modes" on page 139.
0: Data output to PD7-0 in SPP Extended mode dur-
1: Data input from PD7-0 in SPP Extended mode dur-
modes, IRQx is floated. (Default)
tions.
In SPP Extended mode, IRQx is set active on the trail-
ing edge of ACK.
In EPP modes, IRQx follows ACK transitions, or is
set when an EPP time-out occurs.
ing write cycles. (Default)
ing read cycles.