pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 97

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bit 5 - Step
Bit 6 - Reserved
Bit 7 - IRQ Pending
5.3.2
Status Register B (SRB) is a read-only diagnostic register
that is valid only in PS/2 drive mode.
SRB can be read at any time while PS/2 drive mode is ac-
tive. In PC-AT drive mode, all bits are in TRI-STATE during
a microprocessor read.
Bit 0 - Motor 0 Status (MTR0)
Bit 1 - Motor 1 Status (MTR1)
1
1
7
This bit indicates whether or not the head of the Floppy
Disk Drive (FDD) should move during a seek operation.
Its value is the inverse of the STEP disk interface output
signal.
0: STEP is not active, i.e., the head of the FDD
1: STEP is active (low), i.e., the head of the FDD does
This bit signals the completion of the execution phase of
certain FDC commands. Its value reflects the status of
the IRQ signal assigned to the FDC.
0: The IRQ signal assigned to the FDC is not active.
1: The IRQ signal assigned to the FDC is active, i.e.,
This bit indicates the complement of the MTR0 output
pin.
This bit is cleared to 0 by a hardware reset and unaffect-
ed by a software reset.
0: MTR0 not active; motor 0 off
1: MTR0 active; motor 0 on (default)
This bit indicates the complement of the MTR1 output
pin.
This bit is cleared to 0 by a hardware reset and unaffect-
ed by a software reset.
0: MTR0 not active; motor 1 off
1: MTR0 active.; motor 1 on (default)
Reserved
1
1
6
moves. (Default)
not move.
the FDD has completed execution of certain FDC
commands.
Status Register B (SRB)
Reserved
0
5
Drive Select 0 Status
0
4
WDATA
0
3
RDATA
PS/2 Drive Mode
0
2
WGATE
0
1
MTR1
0
0
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
Reset
Required
MTR0
SRB Register
Offset 01h
97
Bit 2 - Write Circuitry Status (WGATE)
Bit 3 - Read Data Status (RDATA)
Bit 4 - Write Data Status (WDATA)
Bit 5 - Drive Select 0 Status
Bits 7,6 - Reserved
5.3.3
DOR is a read/write register that can be written at any time.
It controls the drive select and motor enable disk interface
output signals, enables the DMA logic and contains a soft-
ware reset bit.
The contents of the DOR is set to 00h after a hardware re-
set, and is unaffected by a software reset.
TABLE 5-2 "Drive and Motor Pin Encoding for Four Drive
Configurations and Drive Exchange Support" shows how
the bits of DOR select a drive and enable a motor when the
FDC is enabled (bit 3 of the Function Enable Register 1
(FER1) at offset 00h of logical device 8 is 1) and bit 7 of the
SuperI/O FDC Configuration register at index F0h is 1. Bit
patterns not shown produce states that should not be de-
coded to enable any drive or motor.
When the FDC is enabled and bit 7 of the of the SuperI/O
FDC Configuration register at index F0h is 1, MTR1 pre-
sents a pulse that is the inverse of WR. This pulse is active
whenever an I/O write to address 02h occurs. This pulse is
delayed for between 25 and 80 nsec after the leading edge
of WR. The leading edge of this pulse can be used to clock
data into an external latch (e.g., 74LS175).
This bit indicates the complement of the WGATE output
pin.
0: WGATE not active. The write circuitry of the select-
1: WGATE active. The write circuitry of the selected
If read data was sent, this bit indicates whether an odd
or even number of bits was sent.
Every inactive edge transition of the RDATA disk inter-
face output signal causes this bit to change state.
0: Either no read data was sent or an even number of
1: An odd number of bits of read data was sent.
If write data was sent, this bit indicates whether an odd
or even number of bits was sent.
Every inactive edge transition of the WDATA disk inter-
face output signal causes this bit to change state.
0: Either no write data was sent or an even number of
1: An odd number of bits of write data was sent.
This bit reflects the status of drive select bit 0 in the Dig-
ital Output Register (DOR). See Section 5.3.3 "Digital
Output Register (DOR)".
It is cleared after a hardware reset and unaffected by a
software reset.
0: Either drive 0 or 2 is selected. (Default)
1: Either drive 1 or 3 is selected.
These bits are reserved and are always 1.
ed FDD is enabled.
FDD is disabled. (Default))
bits of read data was sent. (Default)
bits of write data was sent. (Default)
Digital Output Register (DOR)
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