pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 43

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

2.10.1 CS0 Base Address MSB Register
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 60h.
See TABLE 2-7 "Plug and Play (PnP) I/O Space Configu-
ration Registers" on page 31.
2.10.2 CS0 Base Address LSB Register
This read/write register is reset by hardware to 00h. It is the
same as the Plug and Play ISA base address register at in-
dex 61h. See TABLE 2-7 "Plug and Play (PnP) I/O Space
Configuration Registers" on page 31.
2.10.3 CS0 Configuration Register
This read/write register is reset by hardware to 00h. It con-
trols activation of the CS0 signal upon an address match,
when AEN is inactive (low) and the non-masked address
pins match the corresponding base address bits.
0Bh-0Fh
10h-FFh
Second
FIGURE 2-15. SuperI/O CS0 Configuration Register
0
7
Level
Index
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
TABLE 2-24. The Programmable Chip Select
0
Mask Address Pins A11
6
Unaffected by RD/WR
0
5
CS0 Base Address MSB Register R/W 00h
CS1 Base Address MSB Register R/W 00h
CS2 Base Address MSB Register R/W 00h
CS0 Base Address LSB Register R/W 00h
CS1 Base Address LSB Register R/W 00h
CS2 Base Address LSB Register R/W 00h
Assert Chip Select Signal on Read
0
4
CS0 Configuration Register
CS1 Configuration Register
CS2 Configuration Register
Configuration Registers
Assert Chip Select Signal on Write
0
3
Register Name
Mask Address Pin A3
Not Accessible
0
2
Reserved
Reserved
Reserved
Mask Address Pin A2
0
1
Bitmap
Mask Address Pin A1
0
0
Reset
Required
Mask Address Pin A0
CS0 Configuration
Second Level
Type Reset
R/W 00h
R/W 00h
R/W 00h
Index 02h
Register,
-
-
-
-
Configuration
-
-
-
-
43
Bit 0 - Mask Address Pin A0
Bit 1 - Mask Address Pin A1
Bit 2 - Mask Address Pin A2
Bit 3 - Mask Address Pin A3
Bit 4 -
Bit 5 - Assert Chip Select Signal on Read
Bit 6 - Unaffected by RD/WR
Bit 7 - Mask Address Pins A11-A0
2.10.4 Reserved
Attempts to access this register produce undefined results.
2.10.5 CS1 Base Address MSB Register
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 60h.
See TABLE 2-7 "Plug and Play (PnP) I/O Space Configu-
ration Registers" on page 31.
2.10.6 CS1 Base Address LSB Register
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 61h.
See TABLE 2-7 "Plug and Play (PnP) I/O Space Configu-
ration Registers" on page 31.
2.10.7 CS1 Configuration Register
This read/write register is reset by hardware to 00h. It func-
tions like the CS0 Configuration Register described in Sec-
tion 2.10.3 "CS0 Configuration Register" on page 43.
0: A0 is decoded.
1: A0 is not decoded; it is ignored.
0: A1 is decoded.
1: A1 is not decoded (ignored).
0: A2 is decoded.
1: A2 is not decoded; it is ignored.
0: A3 is decoded.
1: A3 is not decoded; it is ignored.
0: Chip select not asserted on address match and
1: Chip select asserted on address match and when
0: Chip select not asserted on address match and
1: Chip select asserted on address match and when
Bits 5 and 4 are ignored when this bit is set.
0: Chip select asserted on address match, qualified
1: Chip select asserted on address match, regardless
0: A11 are decoded.
1: A11 are not decoded; they are ignored.
when WR is active (low).
WR is active (low).
when RD is active (low).
RD is active (low).
by RD or WR pin state and contents of bits 5 and 4.
of RD or WR pin state and regardless of contents
of bits 5 and 4.
Assert Chip Select Signal on Write
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