tda8296 NXP Semiconductors, tda8296 Datasheet - Page 34

• Manufacturer Part Number: tda8296
• Description: Tda8296 Digital Global Standard Low If Demodulator For Analog Tv And Fm Radio
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8296
Product data sheet
9.3.10 V-sync adjustment
9.3.11 CVBS settings
Table 29.
Legend: * = default value.
Table 30.
Legend: * = default value.
Bit
7 and 6 VS_WIDTH[1:0] R/W
5
4 to 0
Bit
7 and 6 -
5 and 4 -
3
2
1
0
Symbol
VS_POL
VS_DEL[4:0]
Symbol
CVBS_EQ_
CTRL
FOR_BLK
AUTO_BLK R/W
-
V_SYNC_DEL register (address 1Ch) bit description
CVBS_SET register (address 1Dh) bit description
Digital global standard low IF demodulator for analog TV and FM radio
All information provided in this document is subject to legal disclaimers.
Access Value Description
R/W
R/W
R/W
R/W
R/W
Rev. 1 — 3 March 2011
Access Value
R/W
R/W
00*
11*
0*
1
0*
1
0*
1
1*
00
01*
10
11
0
1*
0Fh*
not used
must be set to logic 11 or in case of L/L-accent to 01
video equalizer mode control
when active, the video output is always blanked, e.g. for
channel change (forced blank)
when active, the video output is blanked if the horizontal
line lock flag (N_H_LOCK, see
reserved, must be set to logic 1
mode using predefined settings like described in
Table 32
free programmable mode; for details
see
no action
video blanked
auto-blanking off
auto-blanking on
Description
VS_WIDTH determines the width (in horizontal
lines) of the V-sync gating pulse (needed for gating
of tuner RF AGC2)
VS_POL determines the polarity of the V-sync
pulse: if VS_POL = 1, the first edge of the pulse is
positive, else negative.
VS_DEL determines the first edge position of the
output V-sync pulse compared to the beginning of
the vertical blanking interval:
pulse_position
Section 9.3.19
width 1 line (64 μs)
width 2 lines
width 4 lines
width 16 lines
first edge negative
first edge positive
first edge 3 lines after beginning of vertical
interval
=
(
VS_DEL 12
Table
–
) lines
TDA8296
41) is not present
© NXP B.V. 2011. All rights reserved.
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