tda8296 NXP Semiconductors, tda8296 Datasheet - Page 49

• Manufacturer Part Number: tda8296
• Description: Tda8296 Digital Global Standard Low If Demodulator For Analog Tv And Fm Radio
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8296
Product data sheet
9.3.19 Special equalizer functions for group delay and video (CVBS)
To realize special customer demands or accurate compensation of the tuner influence,
the TDA8296 has got freely programmable equalizers for the group delay and video
(CVBS) response.
In
programming of the video equalizer. For each equalizer type an example is given.
Table 58.
Legend: * = default value
[1]
Remark: The group delay equalizer consists of four cascaded all-pass Infinite Impulse
Response (IIR) sections of second order (8th order in sum). The transfer function H(z) of
one section is as follows, while the sampling rate is 13.5 MHz:
GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2 (x = 1 to 4) are defining the linear and
square coefficient of each section, i.e. GD_EQ_SECTx_C1 = b
GD_EQ_SECTx_C2 = b
representation is in two’s complement. There is one sign bit, one magnitude bit and
6 fractional bits. Each fractional bit represents an inverse power of two, so that the highest
value for a coefficient is 2
representation for this value is 01.11 1111 (= 7Fh) and all bits except the sign bit are
logic 1. As two’s complement is chosen, the lowest value for a coefficient is −2, which is
10.00 0000 (= 80h) in the binary representation. So, for the lowest possible value, only the
sign bit is logic 1. The shown default values for GD_EQ_SECTx_C1 and
GD_EQ_SECTx_C2 (x = 1 to 4) implement a flat equalizer response.
Example of
4.43 MHz to 5 MHz on the CVBS signal is wanted, one might realize a characteristic like
shown in
Address Register
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
Table 58
Don’t care if GD_EQ_CTRL = 0; see
Figure
GD_EQ_SECT1_C1
GD_EQ_SECT1_C2
GD_EQ_SECT2_C1
GD_EQ_SECT2_C2
GD_EQ_SECT3_C1
GD_EQ_SECT3_C2
GD_EQ_SECT4_C1
GD_EQ_SECT4_C2
GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2 (x = 1 to 4) register (address 4Bh to
52h) bit description
the programming of the group delay equalizer is explained, in
Table
Digital global standard low IF demodulator for analog TV and FM radio
All information provided in this document is subject to legal disclaimers.
17.
58: If e.g. a flat group delay response up to 4 MHz and −70 ns from
[1]
Rev. 1 — 3 March 2011
.
2
. The coefficients are in signed fixed-point format, the
0
+ 2
−1
H z ( )
+ ... + 2
Table
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
=
-----------------------------------------------------
1
23.
b
+
−6
2
b
+
= 2
1
Symbol
GD_EQ_SECT1_C1[7:0]
GD_EQ_SECT1_C2[7:0]
GD_EQ_SECT2_C1[7:0]
GD_EQ_SECT2_C2[7:0]
GD_EQ_SECT3_C1[7:0]
GD_EQ_SECT3_C2[7:0]
GD_EQ_SECT4_C1[7:0]
GD_EQ_SECT4_C2[7:0]
×
b
1
1
z
×
1 –
− 2
z
+
1 –
−6
b
+
2
= 1.984375. The binary
z
×
2 –
z
2 –
1
and
TDA8296
© NXP B.V. 2011. All rights reserved.
Access Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 60
00h*
00h*
00h*
00h*
00h*
00h*
00h*
00h*
the
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