tda8296 NXP Semiconductors, tda8296 Datasheet - Page 46

• Manufacturer Part Number: tda8296
• Description: Tda8296 Digital Global Standard Low If Demodulator For Analog Tv And Fm Radio
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 53.
Legend: * = default value.
TDA8296
Product data sheet
Address Register
3Fh
40h
41h
42h
PLL_REG07 7
PLL_REG08 7 to 0 MSEL[7:0] R/W
PLL_REG09 7 to 1 NSEL[6:0] R/W
PLL_REG10 7 to 5 -
PLL_REG07, PLL_REG08, PLL_REG09 and PLL_REG10 register (address 3Fh to 42h) bit description
9.3.17 Clock generation (PLL and crystal oscillator)
Table 51.
Legend: * = default value.
Table 52.
Legend: * = default value.
The TDA8296 implements a crystal oscillator which can be used either in Slave mode or
in Oscillator mode (see
input clock, and delivers the system clock of the IC (108 MHz).
The PLL output frequency (108 MHz) can be calculated with the following formula:
Bit
6
5 to 0 -
0
4 to 0 PSEL[4:0] R/W
Bit
7
6 to 1 B_DA_S[5:0] R/W
0
Bit
7
6 to 1 -
0
f
clk(o)(PLL)
Symbol
-
NSEL7
-
Symbol
-
PD_DA_S
Symbol
-
PD_DA_REF
=
AUDIODAC_CTL register (address 36h) bit description
DAC_REF_CLK_CTL register (address 37h) bit description
------------
2 P
f
VCO
×
Digital global standard low IF demodulator for analog TV and FM radio
All information provided in this document is subject to legal disclaimers.
=
Access Value Description
R/W
R/W
R/W
R/W
R/W
f
------------- -
N P
Access Value
R/W
R/W
i
Access Value
R/W
R/W
R/W
×
×
M
Section
Rev. 1 — 3 March 2011
0*
0*
00h*
1Ah*
01h*
0*
000*
01h*
0*
00 0000*
11 1111
0*
1
0*
10 0000* reserved, must be set to logic 10 0000
0*
1
13.7), and a multipurpose PLL which receives XIN as
not used
It programs bit 7 of the N parameter (N = NSEL + 1). N is the
PLL pre-divider. See below for bits NSEL[6:0].
reserved, must be set to 00h
It programs the M parameter (M = MSEL + 1). M is the PLL
feedback-divider.
It programs bits 6 to 0 of the N parameter (N = NSEL + 1).
N is the PLL pre-divider.
reserved, must be set to logic 0
reserved, must be set to logic 000
It programs the P parameter (P = PSEL + 1). P is the PLL
post-divider.
Description
reserved, must be set to logic 0
B_DA_S modifies between 50% to 100% the full scale
DAC output current. See
When HIGH, PD_DA_S sets the sound DAC into its
Power-down mode.
Description
not used
When HIGH, PD_DA_REF sets the reference module
into its Power-down mode.
minimum current setting
maximum current setting
Normal mode
sound DAC Power-down mode
Normal mode
Power-down mode
Section
13.3.
TDA8296
© NXP B.V. 2011. All rights reserved.
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