tda8296 NXP Semiconductors, tda8296 Datasheet - Page 51

• Manufacturer Part Number: tda8296
• Description: Tda8296 Digital Global Standard Low If Demodulator For Analog Tv And Fm Radio
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8296
Product data sheet
Table 60.
Legend: * = default value
[1]
Remark: The overall video (CVBS) equalizer is a symmetric FIR filter with 11 taps. Due to
the symmetry the group delay is constant (linear phase). The transfer function is as
follows, while the sampling rate is 13.5 MHz:
Please note that because of the symmetry h
The mid coefficient h
the coefficients, i.e. CVBS_EQ_COEF0 = h
CVBS_EQ_COEF2 = h
CVBS_EQ_COEF4 = h
h
representation is in two’s complement. There is one sign bit, one magnitude bit and
10 fractional bits. Each fractional bit represents an inverse power of two, so that the
highest value for a coefficient is 2
binary representation for this value is 01.11 1111 1111 (= 7FFh) and all bits except the
sign bit are logic 1. As two’s complement is chosen, the lowest value for a coefficient is
−2, which is 10.00 0000 0000 (= 800h) in the binary representation. So, for the lowest
possible value, only the sign bit is logic 1. The shown default values for
CVBS_EQ_COEFx (x = 0 to 5) implement a flat equalizer response.
Example of
2 MHz is wanted, the following figure (see
Address Register
5Eh
5Fh
60h
61h
62h
0
to h
Don’t care if CVBS_EQ_CTRL = 0; see
5
has got 12-bit quantization. The coefficients are in signed fixed-point format, the
CVBS_EQ_COEF3_HIGH
CVBS_EQ_COEF4_LOW
CVBS_EQ_COEF4_HIGH
CVBS_EQ_COEF5_LOW
CVBS_EQ_COEF5_HIGH
CVBS_EQ_COEFx_LOW and CVBS_EQ_COEFx_HIGH (x = 0 to 5) register
(address 57h to 62h) bit description
Table
H z ( )
Digital global standard low IF demodulator for analog TV and FM radio
All information provided in this document is subject to legal disclaimers.
60: If an attenuation of around 1 dB for video frequencies greater than
=
h
5
0
is only present once. CVBS_EQ_COEFx (x = 0 to 5) are defining
[1]
2
4
+
Rev. 1 — 3 March 2011
.
= h
= h
h
1
×
8
6
, CVBS_EQ_COEF3 = h
z
and CVBS_EQ_COEF5 = h
1 –
+
0
h
+ 2
Table
2
Bit
7 to 4
3 to 0
7 to 0
7 to 4
3 to 0
7 to 0
7 to 4
3 to 0
×
−1
z
2 –
+ ... + 2
32.
Figure
+
0
0
h
= h
3
Symbol
-
CVBS_EQ_COEF3[11:8]
CVBS_EQ_COEF4[7:0]
-
CVBS_EQ_COEF4[11:8]
CVBS_EQ_COEF5[7:0]
-
CVBS_EQ_COEF5[11:8]
= h
…continued
×
10
−10
z
10
18) can be implemented.
3 –
, CVBS_EQ_COEF1 = h
, h
= 2
+
1
3
h
= h
1
4
= h
×
− 2
5
9
. Each of the coefficients
z
7
, h
4 –
,
−10
2
+
= h
= 1.9990234375. The
...
+
8
, h
h
10
3
TDA8296
© NXP B.V. 2011. All rights reserved.
×
= h
Access Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
z
–
1
7
10
= h
and h
9
,
4
0000*
0h*
00h*
0000*
0h*
00h*
0000*
4h*
51 of 87
= h
6
.