tda8296 NXP Semiconductors, tda8296 Datasheet - Page 84

• Manufacturer Part Number: tda8296
• Description: Tda8296 Digital Global Standard Low If Demodulator For Analog Tv And Fm Radio
• Manufacturer: NXP Semiconductors

NXP Semiconductors
21. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. I
Table 11. STANDARD register (address 00h)
Table 12. EASY_PROG register (address 01h)
Table 13. Easy programming values . . . . . . . . . . . . . . . .24
Table 14. DIV_FUNC register (address 02h)
Table 15. ADC_HEADR register (address 03h)
Table 16. PC_PLL_FUNC register (address 04h)
Table 17. DTO_PC_LOW, DTO_PC_MID and
Table 18. Values of DTO_PC per TV standard
Table 19. DTO_SC_LOW, DTO_SC_MID and
Table 20. Values for SSIF mode at 54 MHz sampling
Table 21. FILTERS_1 register (address 0Fh)
Table 22. FILTERS_2 register (address 10h)
Table 23. GRP_DELAY register (address 11h)
Table 24. D_IF_AGC_SET_1 register (address 12h)
Table 25. D_IF_AGC_SET_2 register (address 13h)
Table 26. T_IF_AGC_SET register (address 15h)
Table 27. T_IF_AGC_LIM register (address 16h)
Table 28. T_IF_AGC_FORCE register (address 17h)
Table 29. V_SYNC_DEL register (address 1Ch)
TDA8296
Product data sheet
Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Ordering information . . . . . . . . . . . . . . . . . . . . .5
Pin allocation table . . . . . . . . . . . . . . . . . . . . . . .7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pin type description . . . . . . . . . . . . . . . . . . . . .10
I
I
I
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .25
bit description . . . . . . . . . . . . . . . . . . . . . . . . .25
bit description . . . . . . . . . . . . . . . . . . . . . . . . .26
DTO_PC_HIGH register
(address 09h to 0Bh) bit description . . . . . . . .26
at 54 MHz sampling frequency . . . . . . . . . . . . .27
DTO_SC_HIGH register (address 0Ch to 0Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .27
frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
bit description . . . . . . . . . . . . . . . . . . . . . . . . .28
bit description . . . . . . . . . . . . . . . . . . . . . . . . .30
bit description . . . . . . . . . . . . . . . . . . . . . . . . .31
bit description . . . . . . . . . . . . . . . . . . . . . . . . .32
bit description . . . . . . . . . . . . . . . . . . . . . . . . .32
bit description . . . . . . . . . . . . . . . . . . . . . . . . .32
bit description . . . . . . . . . . . . . . . . . . . . . . . . .33
bit description . . . . . . . . . . . . . . . . . . . . . . . . .33
Address format . . . . . . . . . . . . . . . . . . . . . . . . .13
2
2
2
2
C-bus transfer description . . . . . . . . . . . . . . .13
C-bus transfer description . . . . . . . . . . . . . . .14
C-bus register reference . . . . . . . . . . . . . . . .15
C-bus registers . . . . . . . . . . . . . . . . . . . . . . .18
Digital global standard low IF demodulator for analog TV and FM radio
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 March 2011
Table 30. CVBS_SET register (address 1Dh)
Table 31. CVBS_LEVEL register (address 1Eh)
Table 32. CVBS_EQ register (address 1Fh)
Table 33. SSIF_MUTE register (address 05h)
Table 34. SOUNDSET_1 register (address 20h)
Table 35. SOUNDSET_2 register (address 21h)
Table 36. SOUND_LEVEL register (address 22h)
Table 37. SSIF_LEVEL register (address 23h)
Table 38. ADC_SAT register (address 24h)
Table 39. AFC register (address 25h) bit description . . . 41
Table 40. Calculation of frequency deviation from AFC
Table 41. HVPLL_STAT register (address 26h)
Table 42. D_IF_AGC_STAT register (address 27h)
Table 43. T_IF_AGC_STAT register (address 28h)
Table 44. ALT_FILT_COEF register (address 2Bh)
Table 45. SSIF_AGC_STAT register (address 2Dh)
Table 46. IDENTITY register (address 2Fh)
Table 47. CLB_STDBY register (address 30h)
Table 48. ADC_CTL register (address 33h)
Table 49. ADC_CTL_2 register (address 34h)
Table 50. VIDEODAC_CTL register (address 35h)
Table 51. AUDIODAC_CTL register (address 36h)
Table 52. DAC_REF_CLK_CTL register
Table 53. PLL_REG07, PLL_REG08, PLL_REG09
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 34
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 34
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 35
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 35
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 36
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 36
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 37
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 38
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 39
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 40
value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 42
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46
(address 37h) bit description . . . . . . . . . . . . . . 46
and PLL_REG10 register (address 3Fh to 42h)
TDA8296
© NXP B.V. 2011. All rights reserved.
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