tda8296 NXP Semiconductors, tda8296 Datasheet - Page 71

• Manufacturer Part Number: tda8296
• Description: Tda8296 Digital Global Standard Low If Demodulator For Analog Tv And Fm Radio
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8296
Product data sheet
Fig 31. Hardware reset operation
RST_N
XIN
13.5.1 Hardware reset
13.5.2 Software reset
13.4 ADC connection
13.5 Reset operation
13.6 Application hints
The input signals of the ADC (IF_POS and IF_NEG) can be either AC coupled by means
of two capacitors or connected directly to the inputs (DC coupled). In case of AC coupling,
the DCIN bit (see
dividers between V
input signals.
In case the input signal is DC coupled, the input resistor network can be switched off by
setting the DCIN bit to logic 1. When using the ADC in this mode, the Common mode level
of the input signal should be at (0.5 / 1.2) × V
Please note that during power-down the DC biasing network at the input will be switched
off in order to reduce current consumption. During Sleep mode however the resistor
network will remain active.
After a hardware reset, the registers are set to default (power-on reset values) according
to
A software reset can be done each time something has been programmed. The software
reset does not affect the content of the registers but clears the flip-flops in the design. For
the activation of the software reset see
The DAC application can be adapted to a wide range of application needs. The data sheet
describes 3 different use cases as shown in
The default application (also used for specification) is shown in
supports 75 Ω DC termination for the video CVBS and > 1 kΩ AC/DC termination for the
SSIF or mono audio sound signal. This application is e.g. preferred for device evaluation.
Table
T
XIN
9. M/N standard is the default standard.
immediately in its reset mode
Digital global standard low IF demodulator for analog TV and FM radio
the TDA8296 enters
All information provided in this document is subject to legal disclaimers.
Table
DDA(ADC)(1V2)
Rev. 1 — 3 March 2011
48) should be set to logic 0, which enables the internal resistive
minimum width at LOW is 4
and V
SSD1
Table 47
to take care of the correct DC biasing of the
Figure 23
DDA(ADC)(1V2)
T
XIN
bit CLB.
to
Figure
± 200 mV.
starts after 4 falling edges of XIN
Figure
25.
TDA8296 normal operation
23. This application
TDA8296
© NXP B.V. 2011. All rights reserved.
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