ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 118

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SLAX
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
DATA
I
The I
to be transmitted or the data byte just received. In MASTER TRANSMIT or SLAVE
TRANSMIT modes, the most significant bit of the byte is transmitted first. In MAS-
TER RECEIVE or SLAVE RECEIVE modes, the first bit received is placed in the
most significant bit of the register. After each byte is transmitted, the I2Cx_DR reg-
ister contains the byte that is present in the event of lost arbitration.
I
The I2Cx_CTL register, indicated in
control the interrupts and the master slave relationships on the I
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when
the IFLG is set to 1. When IEN is cleared to 0, the interrupt line always remains
Low.
2
2
C Data Register
C Control Register
2
C Data Register, indicated in
Table 50. I
Value Description
00h–
FFh
Value Description
00h–
FFh
(I2C0_xSAR = C9h, I2C1_xSAR = D9h)
R/W
R/W
(I2C0_DR = CAh, I2C1_DR = DAh)
Least significant 8 bits of the 10-bit extended slave address.
I
7
0
7
0
2
C data byte.
2
Table 51. I
C Extended Slave Address Registers
R/W
R/W
6
0
6
0
PRELIMINARY
2
C Data Registers
R/W
R/W
5
0
5
0
Table
Table 52
R/W
R/W
4
0
4
0
51, contains the data byte/slave address
is a control register that is used to
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
I
2
2
C Serial I/O Interface
C bus.
R/W
R/W
0
0
0
0
104