ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 83

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
UART Recommended Usage
after the received byte with an error reaches the top of the FIFO and is ready to be
read.
A line status interrupt is activated (provided this interrupt is enabled) as long as
the read pointer of the receive FIFO points to the location of the FIFO that con-
tains a byte with the error. The interrupt is immediately cleared when the
UARTx_LSR register is read. The ERR bit of the UARTx_LSR register is active as
long as an error byte is present in the receive FIFO.
UART Modem Status Interrupt
The modem status interrupt is generated if there is any change in state of the
modem status inputs to the UART. This interrupt is cleared when the processor
reads the UARTx_MSR register.
The following is the standard sequence of events that occurs in the eZ80190
device using the UART. A description of each follows.
•
•
•
Module Reset
Upon reset, all internal registers return to their default values. All command status
registers are programmed with their default values and the FIFOs are flushed.
Control Transfers
Based on the application requirement, the data transfer baud rate is determined
and the BRG is configured to generate a 16X clock frequency, provided at the
BRG signal input. Interrupts are disabled and communication control parameters
are programmed in the UARTx_LCTL register. The FIFO configuration is deter-
mined and the receive trigger levels are set in the UARTx_FCTL register. The sta-
tus registers, UARTx_LSR and UARTx_MSR, are read to ensure that no interrupt
sources are active. Interrupts are enabled (except for the transmit interrupt) and
the application is ready to use the module for transmission and reception.
Data Transfers
Transmit. To transmit data, the application enables the transmit interrupt. An
interrupt is immediately expected in response to this interrupt. The application
reads the UARTx_IIR register and determines that the interrupt occurs because of
an empty UARTx_THR register. When the application determines this occurrence,
Module reset
Control transfers to configure UART operation
Data transfers
PRELIMINARY
Universal Asynchronous Receiver/Transmitter
eZ80190 Product Specification
69