ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 156

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Name
DMA0_CTL
DMA1_SAR_L
DMA1_SAR_H
DMA1_SAR_U
DMA1_DAR_L
DMA1_DAR_H
DMA1_DAR_U
DMA1_BC_L
DMA1_BC_H
DMA1_CTL
Bit
Reset
CPU Access
Note: X = Undefined; R/W = Read/Write.
Bit
Position
[7:0]
DMAx_SAR_L,
DMAx_SAR_H,
or
DMAx_SAR_U
DMA Source Address Registers
These two groups of registers hold the 24-bit addresses of the source memory
location for DMA Channel 0 and Channel 1. Depending upon settings within the
DMA Control registers’ SARx_CTL fields, the 24-bit address values can automati-
cally be incremented, decremented, or unchanged following the transfer of each
byte of data. See
DMA0_SAR_L = EEh, DMA0_SAR_H = EFh, DMA0_SAR_U = F0h,
DMA1_SAR_L = F7h, DMA1_SAR_H = F8h, DMA1_SAR_U = F9h
Description
DMA0 Control register
DMA1 Source Address Low Byte register
DMA1 Source Address High Byte register
DMA1 Source Address Upper Byte register
DMA1 Destination Address Low Byte register
DMA1 Destination Address High Byte register
DMA1 Destination Address Upper Byte register
DMA1 Byte Count Low Byte register
DMA1 Byte Count High Byte register
DMA1 Control register
Value Description
00h–
FFh
Table 77. DMA Source Address Registers
Table 76. DMA Registers (Continued)
R/W
Table
X
7
The 2 sets of DMA Source address registers contain the
memory location addresses for the source of the data
transfer. The 24-bit addresses are returned by
{DMAx_SAR_U, DMAx_SAR_H, DMAx_SAR_L}, where x
is either 0 or 1.
77.
R/W
X
6
PRELIMINARY
R/W
X
5
R/W
X
4
R/W
X
3
eZ80190 Product Specification
Access
CPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Direct Memory Access Controller
X
2
R/W
X
1
Reset
Value
00h
00h
00h
00h
XX
XX
XX
XX
XX
XX
R/W
X
0
Register
Address
FBh
FCh
FDh
FEh
F6h
F7h
F8h
F9h
FAh
FFh
142