ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 29

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Pin # Symbol
69
70
71
PC2
SCK1
RTS1
PC3
SS1
CTS1
PC4
DTR1
Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
Function
GPIO Port C
SPI Serial
Clock
Request to
Send
GPIO Port C
Slave Select
Clear to Send Input, Active Low
GPIO Port C
Data Terminal
Ready
Signal Direction
Input/Output
Input/Output
Output, Active Low The RTS1 pin carries the modem-control signal
Input/Output
Input, Active Low
Input/Output
Output, Active Low The DTR1 pin carries the modem-control signal
PRELIMINARY
Description
The PC2 pin can be used for general-purpose I/
O. It can be individually programmed as an input
or output and can also be used individually as an
interrupt input. Each Port C pin, when
programmed as an output, can be selected to be
an open-drain or open-source output. Port C is
multiplexed with one channel of the UZI interface.
SPI serial clock. This signal is multiplexed with
PC2.
from the UART. This signal is multiplexed with
PC2.
The PC3 pin can be used for general-purpose I/
O. It can be individually programmed as an input
or output and can also be used individually as an
interrupt input. Each Port C pin, when
programmed as an output, can be selected to be
an open-drain or open-source output. Port C is
multiplexed with one channel of the UZI interface.
The slave select input line is used to select a
slave device in SPI mode. This signal is
multiplexed with PC3.
The CTS1 pin carries the modem status signal to
the UART. This signal is multiplexed with PC3.
The PC4 pin can be used for general-purpose I/
O. It can be individually programmed as an input
or output and can also be used individually as an
interrupt input. Each Port C pin, when
programmed as an output, can be selected to be
an open-drain or open-source output. Port C is
multiplexed with one channel of the UZI interface.
to the UART. This signal is multiplexed with PC4.
Architectural Overview
15