ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 77

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:0]
BRG_DLR_L
BRG Divisor Latch Registers—High Byte
This register holds the High byte of the 16-bit divisor count loaded by the proces-
sor for baud rate generation. The 16-bit clock divisor value is returned by
{BRGx_DLR_H, BRGx_DLR_L} where x is either 0 or 1 to identify the two avail-
able UZI devices. Upon RESET, the 16-bit BRG divisor value resets to
initial 16-bit divisor value must be between
0000h
the minimum BRG clock divisor ratio is 2.
A write to either the Low- or High-byte registers for the BRG Divisor Latch causes
both bytes to load into the BRG counter, and causes the count to restart.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to
1 to access this register for each UZI device. See
(UARTx_LCTL) on page 75 for more information.
The BRGx_DLR_H registers share the same address space with the UARTx_IER
registers. Bit 7 of the associated UART Line Control register (UARTx_LCTL) must
be set to 1 to enable access for this register within each UZI device.
and
Value
00h–
FFh
Table 24. BRG Divisor Latch Registers—Low Byte
0001h
BRG0_DLR_L = C0h, BRG1_DLR_L = D0h
R/W
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {BRG_DLR_H, BRG_DLR_L}.
7
0
are invalid, and proper operation is not guaranteed. Therefore,
R/W
6
0
PRELIMINARY
R/W
5
0
R/W
4
0
0002h
R/W
3
0
and
UART Line Control Register
R/W
FFFFh
2
0
Universal ZiLOG Interface
R/W
because the values
1
0
R/W
0002h
0
0
. The
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