ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 97

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

eZ80190 Product Specification
83
placed in a high-impedance state if the slave is not selected. When the SPI is not
enabled by the UZI Control register, this signal operates in a high-impedance
state.
Master Out Slave In
The Master Out Slave In (MOSI) pin is configured as an output in a master device
and as an input in a slave device. It is one of the two lines that transfer serial data,
with the most significant bit sent first. When the SPI is not enabled by the UZI
Control register, this signal operates in a high-impedance state.
Slave Select
The active Low Slave Select (SS) input signal is used to select a slave SPI device.
It must be operating in a Low state prior to all data communication and must stay
Low for the duration of the data transfer.
The SS input signal on the master must be in a High state. If the SS signal goes
Low, a Mode Fault error flag (MODF bit) is set in the SPIx_SR register. See
SPI
Status Register
(SPI0_SR =
, SPI1_SR =
) on page 88 for more informa-
B7h
BBh
tion.
When the SPI Clock Phase (CPHA) bit = 0, the shift clock is the OR of SS with
SCK. In this clock phase mode, SS must go High between successive characters
in an SPI message. When CPHA = 1, SS can remain Low for several SPI charac-
ters. In cases where there is only one SPI slave MCU, its SS line could be tied
Low as long as CPHA = 1 CLOCK mode is used. See
SPI Control Register
(SPI0_CTL =
, SPI1_CTL =
) on page 87 for more information on the
B6h
BAh
CPHA bit.
Serial Clock
The Serial Clock (SCK) is used to synchronize data movement both in and out of
the device through its MOSI and MISO pins. The master and slave are each capa-
ble of exchanging a byte of data during a sequence of eight clock cycles. Because
SCK is generated by the master, the SCK pin becomes an input on a slave
device. The SPI contains an internal divide-by-two clock divider. The SPI serial
clock is one-half the frequency of the clock signal created by the UZI Baud Rate
Generator, as shown by the following equation:
System Clock Frequency
SPI Data Transfer Rate (bits/s) =
2 x Baud Rate Generator Divisor
As demonstrated in
Figure 14
and
Table
38, four possible timing relations may be
selected when using control bits CPOL and CPHA in the SPI Control register. See
SPI Control Register
(SPI0_CTL =
, SPI1_CTL =
) on page 87. Both the
B6h
BAh
PS006613-0306
PRELIMINARY
Serial Peripheral Interface