ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 81

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

eZ80190 Product Specification
67
(THRE) bit (bit 5 of the UARTx_LSR register) is set to 1 and an interrupt is sent to
the processor (if interrupts are enabled). The processor can reset this interrupt by
loading data into the UARTx_THR register, which clears the transmitter interrupt.
The transmit shift register places the byte to be transmitted on the TXD signal
serially. The least significant bit of the byte to be transmitted is shifted out first and
the most significant bit is shifted out last. The control logic within the block adds
the asynchronous communications protocol bits to the data byte being transmit-
ted. The transmitter block obtains the parameters for the protocol from the bits
programmed through the UARTx_LCTL register. The TXD output is set to 1 if the
transmitter is idle (it does not contain any data to be transmitted).
The transmitter operates with the Baud Rate Generator (BRG) clock. The data bits
are placed on the TXD output one time every 16 BRG clock cycles. The transmit-
ter block also implements a parity generator and attaches the parity bit with the
byte if programmed to do so.
UART Receiver
The receiver block controls data reception from the RXD signal. The receiver
block implements a receiver shift register, receiver line error condition monitoring
logic and receiver data ready logic. It also implements a parity checker.
The processor reads received data from UARTx_RBR, which is a Read Only reg-
ister. The condition of the UARTx_RBR register is monitored by the DR bit (bit 0 of
the UARTx_LSR register). The DR bit is set to 1 when a data byte is received and
transferred to the UARTx_RBR register from the receiver shift register. The DR bit
is reset only when the processor reads all received data bytes. If the number of
bits received is less than eight, the unused most significant bits of the data byte
read are reset to 0.
The receiver uses the clock from the BRG input of the UZI for receiving data. This
clock must be 16 times the required baud rate. The receiver synchronizes the shift
clock on the falling edge of the RXD input start bit. It then receives a complete
byte according to the set parameters. The receiver also implements logic to detect
framing errors, parity errors, overrun errors, and break signals.
UART Modem Control
The modem control logic provides two outputs and four inputs for handshaking
with the modem. Any change in the modem status inputs, except RI, is detected.
An interrupt can then be generated. For RI, an interrupt is generated only when
the trailing edge of the RI is detected. The module also provides a loop mode for
self-diagnostic purposes.
PS006613-0306
PRELIMINARY
Universal Asynchronous Receiver/Transmitter