mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 173

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mc68ec060

Manufacturer Part Number
mc68ec060
Description
Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Bus Operation
7-18
abled, SAS is asserted during C2 to indicate that the processor immediately begins sam-
pling the terminations signals. Refer to 7.14.1 Acknowledge Termination Ignore State
Capability for details on this special mode.
Assuming that the acknowledge termination ignore state capability is disabled, the pro-
cessor samples the level of TA, TBI, and TCI and registers the current value on the data
bus at the end of C2. If TA is asserted, the transfer terminates and the data is passed to
the appropriate memory unit. If TA is not recognized asserted, the processor ignores the
data and inserts wait states instead of terminating the transfer. The processor continues
to sample TA, TBI, and TCI on successive rising edges of BCLK until TA is recognized
MISCELLANEOUS
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
ATTRIBUTES
SIZ1–SIZ0
BS3–BS0
A31–A4
D31–D0
CIOUT
A1–A0
A3–A2
BCLK
R/W
CLA
SAS
TBI
TIP
TA
TS
Figure 7-15. Line Read Transfer Timing
C1
M68060 USER’S MANUAL
01
C2
C3
10
C4
11
C5
00
MOTOROLA

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