mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 222

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

Figure 7-44 illustrates a functional timing diagram for an arbitration of a relinquish and retry
operation (MC68040 acknowledge termination mode). In Figure 7-44, the processor read
access that begins in C1 is terminated at the end of C2 with a retry request and BG negated,
forcing the processor to relinquish the bus and allow the alternate master to access the bus.
Note that the processor re-asserts BR during C3 since the original access is pending again.
After alternate bus master ownership, the bus is granted to the processor to allow it to retry
the access beginning in C7.
Figure 7-45 is a functional timing diagram for implicit ownership of the bus.
Figure 7-46 illustrates the effect of BGR on bus arbitration activity during locked sequences.
When BGR is asserted while BG is negated, locked sequences can be broken. Otherwise,
the entire locked sequence of bus cycles are completed by the processor before relinquish-
ing the bus.
MOTOROLA
ARBITRATION
ATTRIBUTES
* AM indicates the alternate bus master.
TRANSFER
D31–D0
A31–A0
AM_BG*
AM_BR*
STATE
BCLK
BUS
BTT
BR
BG
TA
BB
TS
AM-EX
C1
ALTERNATE
MASTER
Figure 7-43. Processor Bus Request Timing
AM-EX
C2
AM-EX
C3
M68060 USER’S MANUAL
EX-OWN
C4
EX-OWN
C5
PROCESSOR
EX-OWN
C6
EX-OWN
C7
END-TEN
C8
AM-IMP
C9
ALTERNATE
MASTER
Bus Operation
AM-EX
C10
7-67