mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 73

no-image

mc68ec060

Manufacturer Part Number
mc68ec060
Description
Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc68ec060RC50
Manufacturer:
NXP
Quantity:
1 746
Part Number:
mc68ec060ZU50
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68ec060ZU66
Manufacturer:
MOTOROLA
Quantity:
256
Part Number:
mc68ec060ZU66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68ec060ZU66
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
mc68ec060ZU75
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Memory Management Unit
4.1.2 Translation Control Register
The 32-bit TCR contains control bits which select translation properties. The operating sys-
tem must flush the ATCs before enabling address translation since the TCR accesses and
reset do not flush the ATCs. All unimplemented bits of this register are read as zeros and
must always be written as zeros. The MC68060 always uses long-word transfers to access
this 32-bit register. All bits are cleared by reset. Figure 4-4 illustrates the TCR.
Bits 31–16—Reserved by Motorola. Always read as zero.
E—Enable
P—Page Size
NAD—No Allocate Mode (Data ATC)
NAI—No Allocate Mode (Instruction ATC)
FOTC—1/2-Cache Mode (Data ATC)
4-4
31
0
This bit enables and disables paged address translation.
A reset operation clears this bit. When translation is disabled, logical addresses are used
as physical addresses. The MMU instruction, PFLUSH, can be executed successfully
despite the state of the E-bit. If translation is disabled and an access does not match a
transparent translation register (TTR), the default attributes for the access on the TTR is
defined by the DCO, DUO, DCI, DWO, DUI (default TTR) bits in TCR.
This bit selects the memory page size.
This bit freezes the data ATC in the current state, by enforcing a no-allocate policy for all
accesses. Accesses can still hit, misses will cause a table search. A write access which
finds a corresponding valid read will update the M-bit and the entry remains valid.
This bit freezes the instruction ATC in the current state, by enforcing a no-allocate policy
for all accesses. Accesses can still hit, misses will cause a table search.
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 = Disable
1 = Enable
0 = 4 Kbytes
1 = 8 Kbytes
0 = Disabled
1 = Enable
0 = Disabled
1 = Enable
0 = The data ATC operates with 64 entries.
1 = The data ATC operates with 32 entries.
Figure 4-4. Translation Control Register Format
16
0
M68060 USER’S MANUAL
15
E
14
P
NAD
13
NAI
12
FOTC
11
FITC
10
9
DCO
8
7
DUO
6
DWO
5
MOTOROLA
4 3 2 1 0
DCI
DUI
0

Related parts for mc68ec060