mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 289

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
9-28
Command
$0A
$0B
$0C
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
No operation
Restart the processor
This command restarts the processor after it had been halted by the execution of a HALT instruction
(opcode = $4AC8), or receipt of the $02 (Halt the processor) command.This command must be issued
only when the processor is halted.
Halt the processor
This command forces the processor to gracefully halt. The processor samples for halts once per instruc-
tion and if this command is present, the processor halts execution. The halted state is reflected in the
PST encoding (PST = 11100).
Enable the PULSE instruction to toggle non-pipelined mode
This command enables the PULSE instruction (opcode = $4acc) to toggle the processor between the
non-pipelined mode (allowing single-pipe dispatches) and normal pipeline mode. The PULSE instruction
must be followed by a NOP to ensure proper operation. Refer to command $07 for details of non-pipe-
lined mode, single-pipe dispatch operation. The $04 command negates the effect of this command. This
command must be issued only when the processor is halted.
Reset all non-pipelined modes
This command forces the processor to normal pipeline operation and negates the effect of the $03, $06,
and $07 commands. The $04 command negates the effect of this command. This command must be is-
sued only when the processor is halted.
Reserved
Enable non-pipelined mode (allowing superscalar dispatches)
This command forces the processor into a non-pipelined mode of operation, while allowing superscalar
dispatches (if PCR0 = 1). After an instruction pair is dispatched into the primary and secondary OEPs,
execution of the subsequent instructions is delayed until the original instruction(s) complete execution
and the pipeline is synchronized. The synchronization requires the processor to be in a quiescent state
with all pending memory cycles complete. This implies all write buffers (push and store) are empty. The
$04 command negates the effect of this command. This command must be issued only when the pro-
cessor is halted.
Enable non-pipelined mode (allowing single-pipe dispatches)
This command forces the processor into a non-pipelined mode of operation, while allowing instruction
dispatches into the primary OEP only. After an instruction has been dispatched into the primary OEP,
execution of the subsequent instructions is delayed until the original instruction complete execution and
the pipeline is synchronized. The synchronization requires the processor to be in a quiescent state with
all pending memory cycles complete. This implies all write buffers (push and store) are empty. The $04
command negates the effect of this command. This command must be issued only when the processor
is halted.
Perform CINVA IC operation
This command causes a CINVAIC instruction to be inserted into the primary OEP. This command must
be received while the processor is halted.
Perform CINVA DC operation
This command causes a CINVA DC instruction to be inserted into the primary OEP. This command must
be received while the processor is halted.
Perform CPUSHA IC,DC operation
This command causes a CPUSHA IC,DC instruction to be inserted into the primary OEP. This command
must be issued only when the processor is halted.
Perform CPUSHA DC operation
This command causes a CPUSHA DC instruction to be inserted into the primary OEP. This command
must be issued only when the processor is halted.
Perform PFLUSHA operation
This command causes a PFLUSHA instruction to be inserted into the primary OEP. This command must
be received while the processor is halted.
Table 9-5. Command Summary
M68060 USER’S MANUAL
Command Operation
MOTOROLA