mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 72

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

4.1 MEMORY MANAGEMENT PROGRAMMING MODEL
The memory management programming model is part of the supervisor programming model
for the MC68060. The seven registers that control and provide status information for
address translation in the MC68060 are: the user root pointer register (URP), the supervisor
root pointer register (SRP), the translation control register (TCR), and four independent
transparent translation registers (ITTR0, ITTR1, DTTR0, and DTTR1). Only programs that
execute in the supervisor mode can directly access these registers. Figure 4-2 illustrates the
memory management programming model.
4.1.1 User and Supervisor Root Pointer Registers
The SRP and URP registers each contain the physical address of the translation table’s root,
which the MMU uses for supervisor and user accesses, respectively. The URP points to the
translation table for the current user task. When a new task begins execution, the operating
system typically writes a new root pointer to the URP. A new translation table address
implies that the contents of the ATCs may no longer be valid. Writing a root pointer register
does not affect the contents of the ATCs. A PFLUSH instruction should be executed to flush
the ATCs before loading a new root pointer value, if necessary. Figure 4-3 illustrates the for-
mat of the 32-bit URP and SRP registers. Bits 8–0 of an address loaded into the URP or the
SRP must be zero. Transfers of data to and from these 32-bit registers are long-word trans-
fers.
MOTOROLA
31
31
31
31
31
31
31
31
Figure 4-2. Memory Management Programming Model
Figure 4-3. URP and SRP Register Formats
SUPERVISOR ROOT POINTER
USER ROOT POINTER
M68060 USER’S MANUAL
0
0
0
0
0
0
0
URP
SRP
DTTR0
DTTR1
ITTR0
ITTR1
TCR
USER ROOT POINTER REGISTER
SUPERVISOR ROOT POINTER REGISTER
TRANSLATION CONTROL REGISTER
DATA TRANSPARENT TRANSLATION REGISTER 0
DATA TRANSPARENT TRANSLATION REGISTER 1
INSTRUCTION TRANSPARENT TRANSLATION
REGISTER 0
INSTRUCTION TRANSPARENT TRANSLATION
REGISTER 1
9
8
0
0
Memory Management Unit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4-3
0
0
0