mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 181

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

Bus Operation
7-26
tion of TA, the processor continues the cycle with C3. Otherwise, if TBI was asserted, the
line transfer is burst inhibited and the processor writes the remaining three long words us-
ing long-word write bus cycles. In this case, the processor increments A3 and A2 for each
write, and the new address is placed on the address bus for each bus cycle. Refer to 7.7.3
Byte, Word, and Long-Word Write Cycles for information on long-word writes. If no wait
TBI ASSERTED
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON A31–A0
3) DRIVE UPA1–UPA0, TT1–TT0, TM2–TM0,
4) DRIVE SIZ1–SIZ0 TO LINE
5) ASSERT TS FOR ONE BCLK
6) ASSERT TIP
7) ASSERT SAS IMMEDIATELY IF
8) PLACE DATA ON D31–D0
1) SAMPLE TBI AND TCI
2) INCREMENT A3–A2 IF CLA ASSERTED
CIOUT, TLN1–TLN0, LOCK, LOCKE, BS3–BS0
ACKNOWLEDGE TERMINATION IGNORE
STATE CAPABILITY DISABLED. ELSE,
ASSERT SAS AFTER WRITE PRIMARY
IGNORE STATE COUNTER HAS EXPIRED
1) ASSERT SAS IMMEDIATELY IF
1) INCREMENT A3–A2 IF CLA
2) PLACE DATA ON D31–D0
1) NEGATE LOCK, LOCKE IF
1) NEGATE TIP OR START NEXT
ACKNOWLEDGE TERMINATION
IGNORE STATE CAPABILITY
DISABLED. ELSE, ASSERT SAS
AFTER WRITE SECONDARY
IGNORE STATE COUNTER HAS
EXPIRED.
ASSERTED
NECESSARY
CYCLE
PROCESSOR
4 LW DONE
Figure 7-20. Line Write Cycle Flowchart
TBI NEGATED
M68060 USER’S MANUAL
CONTINUE WITH FIG. 7-21
1) DECODE ADDRESS
2) REGISTER DATA FROM D31–D0
3) ASSERT TA FOR ONE CLOCK
4) ASSERT CLA TO INCREMENT A3–A2
1) DECODE ADDRESS
2) REGISTER DATA FROM D31–D0
3) ASSERT TA FOR ONE BCLK
4) ASSERT CLA TO INCREMENT A3–A2
5) ASSERT TBI OR TCI AS NEEDED
4 LW NOT DONE
SYSTEM
MOTOROLA