mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 185
mc68ec060
Manufacturer Part Number
mc68ec060
Description
Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68EC060.pdf
(416 pages)
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Bus Operation
7-30
recognized asserted, the processor ignores the data and appends a wait state instead of
terminating the transfer. The processor continues to sample TA on successive rising edg-
es of BCLK until TA is recognized as asserted. The registered data is then passed to the
appropriate memory unit. If more than one read cycle is required to read in the operand(s),
C1 and C2 are repeated accordingly.
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
MISCELLANEOUS
Figure 7-23. Locked Bus Cycle for TAS Instruction Timing
ATTRIBUTES
SIZ1–SIZ0
BS3–BS0
D31–D0
A31–A2
LOCKE
CIOUT
A1–A0
LOCK
BCLK
SAS
R/W
TIP
TA
TS
C1
LONG
M68060 USER’S MANUAL
C2
LOCKED TRANSFER
CI
C3
DRIVE
PRE
C4
MOTOROLA
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