isp1760 NXP Semiconductors, isp1760 Datasheet - Page 34

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isp1760

Manufacturer Part Number
isp1760
Description
Hi-speed Universal Serial Bus Host Controller For Embedded Applications
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
[1]
Table 20:
9397 750 13257
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
CONFIGFLAG register: bit allocation
8.2.5 CTRLDSSEGMENT register (R/W: 0030h)
8.2.6 CONFIGFLAG register (R/W: 0060h)
R/W
R/W
R/W
R/W
23
15
31
0
0
7
0
0
reserved
Table 19:
[1]
The Control Data Structure Segment (CTRLDSSEGMENT) register corresponds to the
most significant address bits (63 to 32) for all EHCI data structures. If the 64AC (64-bit
Addressing Capability) field in HCCPARAMS is cleared, then this register is not used and
software cannot write to it (reading from this register returns zero).
If the 64AC (64-bit Addressing Capability) field in HCCPARAMS is set, this register is used
with link pointers to construct 64-bit addresses to EHCI control data structures. This
register is concatenated with the link pointer from either the PERIODICLISTBASE,
ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address.
This register allows the host software to locate all control data structures within the same
4 gigabytes memory segment.
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in
Bit
31 to 14 -
13 to 0
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0 .
[1]
R/W
R/W
R/W
R/W
22
14
30
0
0
6
0
0
Symbol
FRINDEX[13:0] Frame Index: Bits in this register are used for the frame number in the
FRINDEX register: bit description
R/W
R/W
R/W
R/W
21
13
29
0
0
5
0
0
Rev. 01 — 8 November 2004
Description
reserved
SOF packet and as the index into the Frame List. The value in this
register increments at the end of each time frame (for example,
microframe).
R/W
R/W
R/W
R/W
20
12
28
0
0
4
0
0
FRINDEX[7:0]
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
R/W
19
11
27
FRINDEX[13:8]
0
0
3
0
0
Embedded Hi-Speed USB host controller
R/W
R/W
R/W
R/W
18
10
26
0
0
2
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
R/W
R/W
R/W
R/W
17
25
0
9
0
1
0
0
ISP1760
Table
20.
R/W
R/W
R/W
R/W
34 of 105
16
24
0
8
0
0
0
0

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