isp1760 NXP Semiconductors, isp1760 Datasheet - Page 46

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 48:
[1]
9397 750 13257
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
DMA Start Address register: bit allocation
8.3.10 DMA Start Address register (W: 0344h)
8.3.11 Power Down Control register (R/W: 0354h)
31
23
15
W
W
W
W
0
0
0
7
0
Table 47:
This register defines the start address select for the DMA read and write operations. See
Table 48
Table 49:
This register is used to turn off power to the internal blocks of the ISP1760 to obtain
maximum power savings.
Bit
31 to 24
23 to 16
15 to 0
Bit
31 to 16
15 to 0
30
22
14
W
W
W
W
0
0
0
6
0
for the bit allocation.
Edge Interrupt Count register: bit description
DMA Start Address register: bit description
Symbol
MIN_
WIDTH[7:0]
-
NO_OF_
CLK[15:0]
Symbol
-
START_ADDR
_DMA[15:0]
29
21
13
W
W
W
W
0
0
0
5
0
Rev. 01 — 8 November 2004
Description
Minimum Width: Indicates the minimum width between two edge
interrupts in SOFs (1 SOF = 125 s). This is not valid for level
interrupts. A count of zero means that interrupts occur as and when an
event occurs.
reserved
Number of Clocks: Count in number of clocks that the edge interrupt
must be kept asserted on the interface. The default IRQ pulse width is
approximately 500 ns.
Table 50
Description
reserved
Start Address for DMA: The start address for DMA read or write
cycles.
START_ADDR_DMA[15:8]
START_ADDR_DMA[7:0]
28
20
12
W
W
W
W
0
0
0
4
0
reserved
reserved
shows the bit allocation of the register.
[1]
[1]
27
19
11
W
W
W
W
0
0
0
3
0
Embedded Hi-Speed USB host controller
26
18
10
W
W
W
W
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
25
17
W
W
W
W
0
0
9
0
1
0
ISP1760
46 of 105
24
16
W
W
W
W
0
0
8
0
0
0