isp1760 NXP Semiconductors, isp1760 Datasheet - Page 40

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
[1]
9397 750 13257
Product data sheet
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
reserved
R/W
7
0
Table 34:
Bit
31
30 to 16
15
14 to 9
8
7
6
5
4 to 3
2
1
0
DACK_
POL
R/W
6
0
Symbol
ALL_ATX_
RESET
-
ANA_DIGI_OC
-
DATA_BUS_
WIDTH
-
DACK_POL
DREQ_POL
-
INTR_POL
INTR_LEVEL
GLOBAL_INTR
_EN
HW Mode Control register: bit description
DREQ_
POL
R/W
5
0
Rev. 01 — 8 November 2004
Description
All ATX Reset: For debugging purposes (not used normally).
1 — Enable reset, then write back logic 0
0 — No reset.
reserved; write logic 0
Analog Digital Overcurrent: This bit selects analog or digital
overcurrent detection on pins OC1_N, OC2_N and OC3_N.
0 — Digital overcurrent
1 — Analog overcurrent.
reserved; write logic 0
Data Bus Width:
0 — defines a 16-bit data bus width
1 — sets a 32-bit data bus width.
reserved; write logic 0
DACK Polarity:
1 — indicates that the DACK input is active HIGH
0 — indicates active LOW.
DREQ Polarity:
1 — indicates that the DREQ output is active HIGH
0 — indicates active LOW.
reserved; write logic 0
Interrupt Polarity:
0 — active LOW
1 — active HIGH.
Interrupt Level:
0 — INT level triggered
1 — INT is edge triggered. A pulse of certain width is generated.
Global Interrupt Enable: This bit must be set to logic 1 to enable the
IRQ signal assertion.
0 — IRQ assertion is disabled. IRQ will never be asserted,
regardless of other settings or IRQ events.
1 — IRQ assertion is enabled. IRQ will be asserted according to the
Interrupt Enable register, and events setting and occurrence.
R/W
4
0
reserved
[1]
R/W
3
0
Embedded Hi-Speed USB host controller
INTR_POL
R/W
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
LEVEL
INTR_
R/W
1
0
ISP1760
GLOBAL_
INTR_EN
R/W
40 of 105
0
0