lan91c95 Standard Microsystems Corp., lan91c95 Datasheet - Page 10
lan91c95
Manufacturer Part Number
lan91c95
Description
Isa/pcmcia Full Duplex Single-chip Ethernet And Modem Controller With Ram
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LAN91C95.pdf
(144 pages)
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PIN NO.
59, 60,
61, 63,
65, 66,
68-70,
72-74,
76-79
83
98
82
90
91
Ready
nWait
Data Bus
Reset
Address
Latch
nWrite
Enable
Interrupt
nInterrupt
Request
Interrupt 1
NAME
IOCHRDY
SYMBOL
D0-D15
RESET
nWAIT
nIREQ
INTR0
INTR1
DESCRIPTION OF PIN FUNCTIONS
BALE
nWE
OD24 with
IS with
IS with
TYPE
pullup
pullup
pullup
I/O24
O24
O24
10
ISA - Output. Optionally used by the
LAN91C95 to extend host cycles.
PCMCIA - Output. Optionally used by the
LAN91C95 to extend host cycles.
Bidirectional. 16 bit data bus used to access
the LAN91C95 internal registers. The data bus
has weak internal pullups. Supports direct
connection to the system bus without external
buffering.
Input. Active high Reset. This input is not
considered active unless it is active for at least
100ns to filter narrow glitches. A POR circuit
generates an internal reset upon power up for
at least 15msec. All hardware reset references
in this spec relate to the OR function of the
POR and the RESET pin.
ISA - Input. Address strobe. For systems that
require address latching, the falling edge of
BALE latches address lines and nSBHE.
PCMCIA - Write Enable input. Used for writing
into COR and CSR registers as well as
attribute memory space.
ISA - Active high interrupt signal. The interrupt
line selection is determined by the value of INT
SEL1-0 bits in the Configuration Register. This
interrupt is tri-stated when not selected.
PCMCIA - Active low interrupt request output.
Pin acts as a Ready pin during power-up. The
pin should be pulled low within 10us of the
application of the VCC or Reset (which ever
occurs later). It remains low(0) until the CIS is
loaded in the Internal SRAM.
state indicates to the host controller that the
device is ready.
ISA - Output. Active high interrupt signal. The
interrupt line selection is determined by the
value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
selected.
DESCRIPTION
The high(1)
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