lan91c95 Standard Microsystems Corp., lan91c95 Datasheet - Page 82
![no-image](/images/no-image-200.jpg)
lan91c95
Manufacturer Part Number
lan91c95
Description
Isa/pcmcia Full Duplex Single-chip Ethernet And Modem Controller With Ram
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LAN91C95.pdf
(144 pages)
- Current page: 82 of 144
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I/O SPACE - BANK 3
RCV DISCRD - Set to discard a packet being
received. This bit can be used in conjunction with
ERCV THRESHOLD and ERCV INT to process a
packet header while it is being received and sicard
it if the packet is not desired. Setting this bit will
only discard packets that are still in the process of
being received.
If the RCV DISCRD bit is set prior to the end of a
receive packet, RXOVRN bit in the Interrupt Status
Register will be set to indicate that the packet was
discarded and its memory released. If the receive
packet is complete prior to the RCV DISCRD bit
BYTE
BYTE
HIGH
LOW
OFFSET
C
DISCRD
RCV
0
0
EARLY RCV REGISTER
0
0
NAME
1
0
82
1
1
being set, the packet is received normally and RCV
INT bit is set in the Interrupt Status Register. The
RCV DISCRD bit is self-clearing.
ERCV THRESHOLD - Threshold for ERCV
interrupt. Specified in 64 byte multiples. Whenever
the number of bytes written in memory for the
presently received packet exceeds the ERCV
THRESHOLD, ERCV INT bit of the INTERRUPT
STATUS REGISTER is set.
Refer to the PCMCIA Configuration Registers
Description for Banks 4 and 5.
READ/WRITE
0
1
ERCV THRESHOLD
TYPE
0
1
1
1
SYMBOL
ERCV
1
1
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