lan91c95 Standard Microsystems Corp., lan91c95 Datasheet - Page 22

• Manufacturer Part Number: lan91c95
• Description: Isa/pcmcia Full Duplex Single-chip Ethernet And Modem Controller With Ram
• Manufacturer: Standard Microsystems Corp.

(1) This space also allows access to the PCMCIA Configuration Register through Banks 4 and 5 (LAN91C95
only).
Except for the bus interface, the functional behavior
of the LAN91C95 after initial configuration is
identical for ISA and PCMCIA modes.
The LAN91C95 includes an arbitrated shared
memory of 6 kbytes accessed by the CPU. The
MMU unit allocates RAM memory to be used for
transmit and receive packets, using 256 byte
pages.
The arbitration is transparent to the CPU in every
sense. There is no speed penalty for ISA type of
machines due to arbitration.
restrictions on what locations can be accessed at
any time. RAM accesses as well as MMU requests
are arbitrated.
The RAM is accessed by mapping it into I/O space
for sequential access.
accesses
commands, I/O accesses are not arbitrated.
The I/O space is 16 bits wide. Provisions for 8 bit
systems are handled by the bus interface.
In the system memory space, up to 64 kbytes are
decoded by the LAN91C95 as expansion ROM.
The ROM expansion area is 8 bits wide.
PCMCIA
Attribute
Memory
PCMCIA
Configuration
Registers
Modem I/O
Space
Ethernet I/O
Space (1)
and
SIGNALS USED
nIORD/nIOWR
nIORD/nIOWR
the
nOE/nWE
nOE/nWE
MMU
Except for the RAM
Table 3 - LAN91C95 Address Spaces
There are no
request/release
ISA
N
N
Y
Y
PCMCIA
Y
Y
Y
Y
22
Device configuration is done using a serial
EEPROM, with support for modifications to the
EEPROM at installation time. A Flash ROM is
supported for PCMCIA attribute memory.
The CSMA/CD core implements the 802.3 MAC
layer protocol. It has two independent interfaces,
the data path and the control path. Both interfaces
are 16 bits wide.
The control path provides a set of registers used to
configure and control the block. These registers
are
LAN91C95’s I/O space.
sequential access nature and typically works in one
direction at any given time. An internal DMA type
of interface connects the data path to the device
RAM through the arbiter and MMU.
The CSMA/CD data path interface is not accessible
to the host CPU.
The internal DMA interface can arbitrate for RAM
access and request memory from the MMU when
necessary.
An encoder/decoder block interfaces the CSMA/CD
block on the serial side. The encoder will do the
Manchester encoding of the transmit data at 10
ON-CHIP
(external
ROM)
N
Y
N
Y
accessible
Up to 32k
locations, only
even bytes are
usable
64 locations, only
even bytes are
usable
8 locations
16 locations
DEPTH
by
the
The data path is of
CPU
8 bits on even
addresses
8 bits
8 bit
8 or 16 bits
through
WIDTH
the