lan91c95 Standard Microsystems Corp., lan91c95 Datasheet - Page 70

• Manufacturer Part Number: lan91c95
• Description: Isa/pcmcia Full Duplex Single-chip Ethernet And Modem Controller With Ram
• Manufacturer: Standard Microsystems Corp.

I/O SPACE - BANK2
This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO
control. The three command bits determine the command issued as described below:
COMMAND SET:
000
001
010
011
100
101
xyz
OFFSET
BYTE
BYTE
HIGH
LOW
0
0)
1)
2)
3)
4)
5)
NOOP - NO OPERATION
ALLOCATE MEMORY FOR TX - N2,N1,N0 defines the amount of memory requested as (value
+ 1) * 256 bytes. Namely N2,N1,N0 = 1 will request 2 * 256 = 512 bytes. Valid range for
N2,N1,N0 is 0 through 5. A shift-based divide by 256 of the packet length yields the appropriate
value to be used as N2,N1,N0. Immediately generates a completion code at the ALLOCATION
RESULT REGISTER. Can optionally generate an interrupt on successful completion. The
allocation time can take worst case (N2, N1, N0 + 2) * 200ns.
RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts,
resets packet FIFO pointers.
REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has completed
processing of present receive frame. This command removes the receive packet number from
the RX FIFO and brings the next receive frame (if any) to the RX area (output of RX FIFO).
REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all memory used by
the packet presently at the RX FIFO output.
RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the
PACKET NUMBER REGISTER. Should not be used for frames pending transmission.
Typically used to remove transmitted frames, after reading their completion status. Can be
used following 3) to release receive packet memory in a more flexible way than 4).
x
MMU COMMAND REGISTER
COMMAND
y
NAME
z
0
70
BUSY Bit Readable
0
WRITE ONLY
TYPE
N2
N1
SYMBOL
MMUCR
N0/BUSY
0