lan91c95 Standard Microsystems Corp., lan91c95 Datasheet - Page 73

• Manufacturer Part Number: lan91c95
• Description: Isa/pcmcia Full Duplex Single-chip Ethernet And Modem Controller With Ram
• Manufacturer: Standard Microsystems Corp.

I/O SPACE - BANK2
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The
packet numbers to be processed by the interrupt service routines are read from this register.
REMPTY - No receive packets queued in the RX
FIFO. For polling purposes, uses the RCV_INT bit
in the Interrupt Status Register.
TOP OF RX FIFO PACKET NUMBER - Packet
number presently at the output of the RX FIFO.
Only valid if REMPTY is clear. The packet is
removed
Commands 3) or 4).
TEMPTY - No transmit packets in completion
queue. For polling purposes, uses the TX_INT bit in
the Interrupt Status Register.
OFFSET
BYTE
BYTE
HIGH
LOW
4
from
REMPTY
TEMPTY
1
1
the
RX
FIFO PORTS REGISTER
FIFO
0
0
NAME
using
0
0
MMU
73
0
0
TX DONE PACKET NUMBER - Packet number
presently at the output of the TX Completion FIFO.
Only valid if TEMPTY is clear. The packet is
removed when a TX INT acknowledge is issued.
NOTE: For software compatibility with future
versions, the value read from each FIFO register is
intended to be written into the PNR as is, without
masking higher bits (provided TEMPTY and
REMPTY = 0 respectively).
TX DONE PACKET NUMBER
RX FIFO PACKET NUMBER
READ ONLY
0
0
TYPE
0
0
0
0
SYMBOL
FIFO
0
0