lan91c95 Standard Microsystems Corp., lan91c95 Datasheet - Page 85

• Manufacturer Part Number: lan91c95
• Description: Isa/pcmcia Full Duplex Single-chip Ethernet And Modem Controller With Ram
• Manufacturer: Standard Microsystems Corp.

1 ISSUE ALLOCATE MEMORY FOR TX - N
2 WAIT
3 LOAD TRANSMIT DATA - Copy the TX packet
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
5
6
7 SERVICE INTERRUPT - Read Interrupt Status
BYTES - the MMU attempts to allocate N bytes
of RAM.
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
number into the Packet Number Register.
Write the Pointer Register, then use a block
move operation from the upper layer transmit
queue into the Data Register.
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
Register. If it is a transmit interrupt, read the TX
Done Packet Number from the FIFO Ports
Register. Write the packet number into the
Packet Number Register.
status word is now readable from memory. If
the status word shows successful transmission,
issue RELEASE packet number command to
free up the memory used by this packet.
Remove packet number from completion FIFO
by writing TX INT Acknowledge Register.
FOR
SUCCESSFUL
S/W DRIVER
TYPICAL FLOW OF EVENTS FOR TRANSMIT
The corresponding
COMPLETION
85
The enqueued packet will be transferred to the
CSMA/CD block as a function of TXENA (n
TCR) bit and of the deferral process (in half
duplex mode) state.
Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FIFO into
the TX completion FIFO. Interrupt is generated
by the TX completion FIFO being not empty.
CSMA/CD SIDE