mfrc531 NXP Semiconductors, mfrc531 Datasheet - Page 10
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mfrc531
Manufacturer Part Number
mfrc531
Description
Iso/iec 14443 Reader Ic
Manufacturer
NXP Semiconductors
Datasheet
1.MFRC531.pdf
(116 pages)
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NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
9.1.4.1 SPI read data
Table 6.
Figure 6
Remark: The SPI implementation for MFRC531 conforms to the SPI standard and
ensures that the MFRC531 can only be addressed as a slave.
The structure shown in
up to n-data bytes. The first byte sent defines both, the mode and the address.
Table 7.
The address byte must meet the following criteria:
As shown in
MFRC531 pins
ALE
A2
A1
A0
NRD
NWR
NCS
D7 to D1
D0
Pin
MOSI
MISO
Fig 6.
•
•
•
the Most Significant Bit (MSB) of the first byte sets the mode. To read data from the
MFRC531 the MSB is set to logic 1
bits [6:1] define the address
the Least Significant Bit (LSB) should be set to logic 0.
shows the microprocessor connection to the MFRC531 using SPI.
Connection to microprocessor: SPI
SPI compatibility
SPI read data
Table
8, all the bits of the last byte sent are set to logic 0.
Byte 0
address 0
XX
Rev. 3.4 — 26 January 2010
Table 7
056634
must be used to read data using SPI. It is possible to read
LOW
SCK
LOW
MOSI
MISO
NSS
Byte 1
address 1 address 2 ...
data 0
Byte 2
data 1
SPI pins
NSS
SCK
LOW
MOSI
HIGH
HIGH
LOW
do not connect
MISO
NCS
A2
A1
A0
D0
ALE
MFRC531
001aal223
...
...
Byte n
address n
data n − 1
ISO/IEC 14443 reader IC
MFRC531
© NXP B.V. 2010. All rights reserved.
Byte n + 1
00
data n
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