mfrc531 NXP Semiconductors, mfrc531 Datasheet - Page 6

• Manufacturer Part Number: mfrc531
• Description: Iso/iec 14443 Reader Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 3.
[1]
[2]
[3]
MFRC531_34
Product data sheet
PUBLIC
Pin
13
13 to 20
21
22
23
24
25
26
27
28
29
30
31
32
[3]
[3]
[3]
Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.
The SLRC400 uses pin name SIGOUT for pin MFOUT. The MFRC531 functionality includes test functions for the SLRC400 using pin
MFOUT.
These pins provide different functionality depending on the selected microprocessor interface type (see
detailed information).
[3]
Pin description
Symbol
D0
D0 to D7
AD0 to AD7
ALE
AS
nAStrb
NSS
A0
nWait
MOSI
A1
A2
SCK
DVDD
AVDD
AUX
AVSS
RX
VMID
RSTPD
OSCOUT
…continued
Type
O
I/O
I/O
I
I
I
I
I
O
I
I
I
I
P
P
O
G
I
P
I
O
[1]
Description
SPI master in, slave out output
8-bit bidirectional data bus input/output on pins D0 to D7
8-bit bidirectional address and data bus input/output on pins AD0 to AD7
address latch enable input for pins AD0 to AD5; HIGH latches the internal address
address strobe input for pins AD0 to AD5; HIGH latches the internal address
not address strobe input for pins AD0 to AD5; LOW latches the internal address
not slave select strobe input for SPI communication
address line 0 is the address register bit 0 input
address line 1 is the address register bit 1 input
address line 2 is the address register bit 2 input
SPI serial clock input
digital power supply
analog power supply for pins OSCIN, OSCOUT, RX, VMID and AUX
auxiliary output is used to generate analog test signals. The output signal is
selected using the TestAnaSelect register’s TestAnaOutSel[4:0] bits
receiver input: used as the card response input. The carrier is load modulated at
13.56 MHz, drawn from the antenna circuit
internal reference voltage pin provides the internal reference voltage as a supply
Remark: It must be connected to a 100 nF block capacitor connected between pin
VMID and ground
reset and power-down input:
not wait output:
SPI master out, slave in
analog ground
crystal oscillator output for the oscillator’s inverting amplifier
LOW starts an access cycle
HIGH ends an access cycle
HIGH: the internal current sinks are switched off, the oscillator is inhibited and
the input pads are disconnected
LOW (negative edge): start internal reset phase
Rev. 3.4 — 26 January 2010
056634
ISO/IEC 14443 reader IC
Section 9.1 on page 7
MFRC531
© NXP B.V. 2010. All rights reserved.
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