mfrc531 NXP Semiconductors, mfrc531 Datasheet - Page 33

• Manufacturer Part Number: mfrc531
• Description: Iso/iec 14443 Reader Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
Fig 11. Receiver circuit block diagram
RX
ClkQDelay[4:0]
9.10.2.1 Automatic Q-clock calibration
DEMODULATOR
9.10.1 Receiver circuit block diagram
9.10.2 Receiver operation
CONVERSION
I-clock
13.56 MHz
I TO Q
ClkQCalib
The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90° between them. Both resulting subcarrier signals are amplified, filtered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
Figure 11
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see
The demodulated signal is amplified by an adjustable amplifier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
The signal can be observed on its way through the receiver as shown in
signal at a time can be routed to pin AUX using the TestAnaSelect register as described in
Section 15.2.2 on page
In general, the default settings programmed in the StartUp initialization file are suitable for
device to MIFARE card data communication. However, in some environments specific
user settings will achieve better performance.
The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
and a 90° phase-shifted quadrature signal (Q-clock). To achieve the optimum
demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90°. After
the reset phase, a calibration procedure is automatically performed.
Q-clock
VRxFollI
ClkQ180Deg
clock
VRxFollQ
shows the block diagram of the receiver circuit. The receiving process can be
Gain[1:0]
VRxAmpI
Section 9.10.2.1 on page
VRxAmpQ
Rev. 3.4 — 26 January 2010
103.
CORRELATION
BitPhase[7:0]
CIRCUITRY
056634
TestAnaOutSel
to
VCorrDI
VCorrNI
33).
VCorrDQ
VCorrNQ
MinLevel[3:0]
CollLevel[3:0]
VEvalR
EVALUATION
CIRCUITRY
DIGITIZER
AND
RxWait[7:0]
ISO/IEC 14443 reader IC
VEvalL
MFRC531
RcvClkSell
© NXP B.V. 2010. All rights reserved.
Figure
001aak615
s_valid
s_data
s_coll
s_clock
11. One
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